Yen-Tai Lai

31 papers A* 1A 1C 6Journal 16Unranked 7
YearRankTypeTitle / Venue / Authors
2016 J jnl
A High-Throughput JPEG XR Encoder.
J. Signal Process. Syst.
Chao-Feng Tseng, Yen-Tai Lai
2016 J jnl
Fast coding unit decision and mode selection for intra-frame coding in high-efficiency video coding.
IET Image Process.
Chao-Feng Tseng, Yen-Tai Lai
2014 J jnl
Design of a 1-GSample/s 9-b double sampling track-and-hold amplifier in BiCMOS technology.
Int. J. Circuit Theory Appl.
Hung-Yi Lin, Yen-Tai Lai
2013 J jnl
Design of Low Power Two-phase CMOS Buffer for Large capacitive loading Applications.
J. Circuits Syst. Comput.
Hung-Yi Lin, Yen-Tai Lai
2013 J jnl
Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs.
J. Circuits Syst. Comput.
Chi-Chou Kao, Yen-Tai Lai
2013 J jnl
Power minimization for dynamically reconfigurable FPGA partitioning.
ACM Trans. Embed. Comput. Syst.
Tzu-Chiang Tai, Yen-Tai Lai
2012 — conf
Laplacian-based H.264 intra-prediction mode decision.
CHINACOM
Chi-Chou Kao, Yen-Tai Lai, Chao-Feng Tseng
2011 J jnl
A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning.
ACM Trans. Reconfigurable Technol. Syst.
Tzu-Chiang Tai, Yen-Tai Lai
2011 J jnl
A low distortion CMOS continuous-time common-mode feedback circuit.
Int. J. Circuit Theory Appl.
Yen-Tai Lai, Hung-Yi Lin
2010 J jnl
A Performance-Driven Rotational Invariant Image Retrieval System.
J. Inf. Sci. Eng.
Yen-Tai Lai, Chi-Chou Kao, Tzu-Chiang Tai, Wen-Chun Yeh
2010 J jnl
An efficient reflection invariance region-based image retrieval framework.
Int. J. Imaging Syst. Technol.
Chi-Chou Kao, Yen-Tai Lai, Chia-Hui Lin
2009 C conf
A Novel Digital Pixel Sensor System.
ISCAS
Yen-Tai Lai, Chia-Nan Yeh, Chi-Chou Kao
2008 C conf
A novel flash analog-to-digital converter.
ISCAS
Chia-Nan Yeh, Yen-Tai Lai
2006 C conf
Low power readout control circuit for high resolution CMOS image sensor.
ISCAS
Chia-Nan Yeh, Yen-Tai Lai
2005 J jnl
An efficient algorithm for finding the minimal-area FPGA technology mapping.
ACM Trans. Design Autom. Electr. Syst.
Chi-Chou Kao, Yen-Tai Lai
2005 — conf
BDD decomposition for mixed CMOS/PTL logic circuit synthesis.
ISCAS (6)
Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu
2005 — conf
Placement for the reconfigurable datapath architecture.
ISCAS (2)
Yen-Tai Lai, Hsin-Ya Lai, Chia-Nan Yeh
2004 — conf
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.
ASP-DAC
Chi-Chou Kao, Yen-Tai Lai
2003 — conf
A technology mapping algorithm for heterogeneous FPGAs.
ASP-DAC
Chi-Chou Kao, Yen-Tai Lai
2002 C conf
Design of the ordinary differential equation solver in the Yau filtering system.
ACC
Yen-Tai Lai, Stephen S.-T. Yau, Ping-Hua Chen
2001 J jnl
Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lih-Yang Wang, Yen-Tai Lai
1999 — conf
A quadratic programming method for interconnection crosstalk minimization.
ISCAS (6)
Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh
1999 — conf
A routability and performance driven technology mapping algorithm for LUT based FPGA designs.
ISCAS (1)
Chi-Chou Kao, Yen-Tai Lai
1997 J jnl
Hierarchical interconnection structures for field programmable gate arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Tai Lai, Ping-Tsung Wang
1995 J jnl
Performance-directed compaction for VLSI symbolic layouts.
Comput. Aided Des.
Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang
1994 C conf
A High Performance FPGA with Hierarchical Interconnection Structure.
ISCAS
Ping-Tsung Wang, Kun-Nen Chen, Yen-Tai Lai
1993 A conf
A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths.
ICCAD
Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang
1993 C conf
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths.
ISCAS
Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang
1990 J jnl
A Theory of Rectangular Dual Graphs.
Algorithmica
Yen-Tai Lai, Sany M. Leinwand
1988 J jnl
Algorithms for floorplan design via rectangular dualization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yen-Tai Lai, Sany M. Leinwand
1984 A* conf
An algorithm for building rectangular floor-plans.
DAC
Sany M. Leinwand, Yen-Tai Lai