Yen-Lung Chen

21 papers A* 2A 2C 1Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 28nm Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.
IEEE Trans. Biomed. Circuits Syst.
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2024 J jnl
A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring.
IEEE J. Solid State Circuits
Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang
2023 — conf
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.
ISSCC
Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2023 J jnl
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping.
IEEE Trans. Biomed. Circuits Syst.
Chung-Hsuan Yang, Yi-Chung Wu, Yen-Lung Chen, Chao-Hsi Lee, Jui-Hung Hung, Chia-Hsiang Yang
2021 — conf
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring.
A-SSCC
Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang
2021 J jnl
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.
IEEE J. Solid State Circuits
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2021 J jnl
A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome.
IEEE Trans. Parallel Distributed Syst.
Yen-Lung Chen, Bo-Yi Chang, Chia-Hsiang Yang, Tzi-Dar Chiueh
2020 — conf
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.
ISSCC
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
2016 C conf
Wave digital filter based analog circuit emulation on FPGA.
ISCAS
Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He
2015 — conf
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits.
ASP-DAC
Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He
2015 — conf
Layout-aware analog synthesis environment with yield consideration.
ISQED
Hsin-Ju Chang, Yen-Lung Chen, Conan Yeh, Chien-Nan Jimmy Liu
2015 A conf
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).
FPGA
Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He
2014 A* conf
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage.
DAC
Wei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He
2014 — conf
Robust guidance law design for UAVs.
ICCA
Yung-Yue Chen, Yen-Lung Chen, Bo-Hui Zhou
2014 J jnl
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li
2014 — conf
Simultaneous optimization for low dropout regulator and its error amplifier with process variation.
VLSI-DAT
Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu
2013 — conf
A layout-aware automatic sizing approach for retargeting analog integrated circuits.
VLSI-DAT
Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu
2013 A conf
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects.
DATE
Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, Chien-Nan Jimmy Liu
2013 — conf
LASER: layout-aware analog synthesis environment on laker.
ACM Great Lakes Symposium on VLSI
Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen
2012 J jnl
A fast heuristic approach for parametric yield enhancement of analog designs.
ACM Trans. Design Autom. Electr. Syst.
Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai
2010 A* conf
Behavior-level yield enhancement approach for large-scaled analog circuits.
DAC
Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu