Yen-Jen Chang

44 papers A 6C 1Misc 2Journal 26Unranked 9
YearRankTypeTitle / Venue / Authors
2026 J jnl
Reconfigurable 9T Static RAM Design With Dynamic Switching Between Content-Addressable Memory and In-Memory Computing.
IEEE Trans. Circuits Syst. Artif. Intell.
Yen-Jen Chang, Kun-Lin Tsai, Xu-Yao Chen
2025 J jnl
Multilogic Sense Amplifier With a Circuit for Dynamic Reference Voltage Generation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yen-Jen Chang, Kun-Lin Tsai, Chun Cheng, Xu-Yao Chen
2024 J jnl
Content-aware malicious webpage detection using convolutional neural network.
Multim. Tools Appl.
Yen-Jen Chang, Kun-Lin Tsai, Wei-Cheng Jiang, Meng-Kun Liu
2024 J jnl
Modified YOLO network model for metaphase cell detection in antinuclear antibody images.
Eng. Appl. Artif. Intell.
Yen-Jen Chang, Yi-Da Wu, Yu-Lin Liao, Chien-Ho Wang, Yen-Ching Wu
2024 J jnl
Target-Aware Yield Prediction (TAYP) Model Used to Improve Agriculture Crop Productivity.
IEEE Trans. Geosci. Remote. Sens.
Yen-Jen Chang, Ming-Hsin Lai, Chien-Ho Wang, Yu-Shun Huang, Jason Lin
2023 J jnl
Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yen-Jen Chang, Shih-Hsiang Chen
2021 J jnl
Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kun-Lin Tsai, Yen-Jen Chang, Chien-Ho Wang, Cheng-Tse Chiang
2021 J jnl
Data Retention-Based Low Leakage Power TCAM for Network Packet Routing.
IEEE Trans. Circuits Syst. II Express Briefs
Yen-Jen Chang, Kun-Lin Tsai, Yu-Cheng Cheng
2020 J jnl
A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism.
IEEE Access
Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, Chun-Huo Hsiao
2020 J jnl
Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment.
Comput. Electr. Eng.
Yen-Jen Chang, Kun-Lin Tsai, Yu-Cheng Cheng, Meng-Rong Lu
2019 J jnl
Imprecise 4-2 compressor design used in image processing applications.
IET Circuits Devices Syst.
Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, Tung-Chi Wu
2017 — conf
Radix-4 adder design with refined carry.
DSC
Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, Yen-Jen Chang
2016 — conf
Low leakage mask vertical control TCAM for network router.
APCCAS
Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, Yen-Jen Chang
2015 J jnl
Master-Slave Match Line Design for Low-Power Content-Addressable Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Jen Chang, Tung-Chi Wu
2014 J jnl
Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kun-Lin Tsai, Yen-Jen Chang, Yu-Cheng Cheng
2013 J jnl
Improving the performance of port range check for network packet filtering.
ACM Trans. Design Autom. Electr. Syst.
Yen-Jen Chang, Hsiang-Yu Lu
2013 J jnl
Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yen-Jen Chang, Kun-Lin Tsai, Hsiang-Jen Tsai
2013 — conf
Low-power content-addressable memory design using a double match-line (DML) architecture.
MWSCAS
Ya-Chun Lin, Yen-Jen Chang, Tung-Chi Wu
2011 — conf
A low-power TCAM design using mask-aware match-line (MAML) technique.
ACM Great Lakes Symposium on VLSI
Yen-Jen Chang, Tung-Chi Wu
2011 J jnl
Fast color-spatial feature based image retrieval methods.
Expert Syst. Appl.
Chuen-Horng Lin, Der-Chen Huang, Yung-Kuan Chan, Kai-Hung Chen, Yen-Jen Chang
2010 J jnl
Don't-Care Gating (DCG) TCAM Design Used in Network Routing Table.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Jen Chang
2010 J jnl
Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power.
IEEE Trans. Circuits Syst. II Express Briefs
Yen-Jen Chang
2009 J jnl
A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup.
IEEE Trans. Circuits Syst. II Express Briefs
Yen-Jen Chang
2009 A conf
A Novel High Performance Ternary CAM (TCAM) for LPM.
ESA
Yung-Feng Cheng, Yen-Jen Chang
2009 A conf
Low Power Selected Gating Frame Buffer (SGFB) Design.
ESA
Jin-Wei Yang, Yen-Jen Chang
2008 — conf
Exploiting frequent opcode locality for power efficient instruction cache.
ACM Great Lakes Symposium on VLSI
Yen-Jen Chang
2008 J jnl
Hybrid-Type CAM Design for Both Power and Performance Efficiency.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Jen Chang, Yuan-Hong Liao
2007 A conf
Improve CAM power efficiency using decoupled match line scheme.
DATE
Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan
2007 J jnl
Two New Techniques Integrated for Energy-Efficient TLB Design.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Jen Chang, Maofeng Lan
2006 Misc conf
An Alternative Real-Time Filter Scheme to Block Buffering.
VLSI Design
Yen-Jen Chang
2006 J jnl
An Energy-Efficient BTB Lookup Scheme for Embedded Processors.
IEEE Trans. Circuits Syst. II Express Briefs
Yen-Jen Chang
2006 A conf
An ultra low-power TLB design.
DATE
Yen-Jen Chang
2006 — conf
Lazy BTB: reduce BTB energy consumption using dynamic profiling.
ASP-DAC
Yen-Jen Chang
2005 J jnl
Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories.
IEEE Micro
Yen-Jen Chang, Feipei Lai
2004 Misc conf
Enhanced object management for high performance web proxies.
SAC
Yen-Jen Chang, Yung-Ching Weng, Feipei Lai
2004 A conf
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.
DATE
Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
2004 J jnl
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
2003 A conf
A power-aware SWDR cell for reducing cache write power.
ISLPED
Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
2003 J jnl
Design and analysis of low-power cache using two-level filter scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai
2002 — conf
An Efficient Two-Level Filter Scheme for Low Power Cache.
IWLS
Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
2002 C conf
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.
ICCD
Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
2002 J jnl
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn
2002 — conf
Energy analysis of bipartition architecture for pipelined circuits.
APCCAS (2)
Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai
2002 — conf
Paged cache: an efficient partition architecture for reducing power, area and access time.
APCCAS (2)
Yen-Jen Chang, Feipei Lai