Yehea I. Ismail

165 papers A* 10A 19B 1C 28Journal 47Unranked 57

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	Thermal Resistance Model for Standard CMOS Thermoelectric Generator. IEEE Access Eman F. Sawires, Mohamed I. Eladawy, Yehea I. Ismail, Hamdy Abdelhamid
2018	J	`jnl`	Two-dimensional models for quantum effects on short channel electrostatics of lightly doped symmetric double-gate MOSFETs. IET Circuits Devices Syst. Rana Y. El Kashlan, Hamdy Abd Elhamid, Yehea I. Ismail
2017	—	`conf`	Clock signal characterization for signal integrity. CCWC Ahmed Saeed, Alaa E. El-Rouby, Yehea I. Ismail, Hani F. Ragai
2016	—	`conf`	A 0.4V 90nm CMOS subthreshold current conveyor. CCECE Mohammed A. Eldeeb, Yehya H. Ghallab, Hassan El-Ghitani, Yehea I. Ismail
2016	J	`jnl`	Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication. IEEE Trans. Circuits Syst. II Express Briefs Wameedh Nazar Flayyih, Khairulmizam Samsudin, Shaiful Jahari Hashim, Yehea I. Ismail, Fakhrul Zaman Rokhani
2016	—	`conf`	Design guidelines for embeded NoCs on FPGAs. ISQED Noha Gamal, Hossam A. H. Fahmy, Yehea I. Ismail, Hassan Mostafa
2016	—	`conf`	Design guidelines for soft implementations to embedded NoCs of FPGAs. IDT Noha Gamal, Hossam A. H. Fahmy, Yehea I. Ismail, Tawfik Ismail, Mohamed Mohie El-Din, Hassan Mostafa
2016	C	`conf`	Five-level hybrid DC-DC converter with enhanced light-load efficiency. ISCAS Abdullah Abdulslam, Farid El-Sehrawy, Yehea I. Ismail
2016	J	`jnl`	On the use of a programmable front-end for multi-band/multi-standard applications. Microelectron. J. Hoda Abdelsalam, Emad Hegazi, Hassan Mostafa, Yehea I. Ismail
2015	—	`conf`	5-Level buck converter with reduced inductor size suitable for on-chip integration. ICEAC Abdullah Abdulslam, Yehea I. Ismail
2015	J	`jnl`	A 76.8 MHz temperature compensated MEMS reference oscillator for wireless handsets. Microelectron. J. Ali Kourani, Emad Hegazi, Yehea I. Ismail
2015	—	`conf`	A CMOS based operational floating current conveyor and its applications. ICECS Nermine M. Edward, Yehya H. Ghallab, Hassan Mostafa, Yehea I. Ismail
2015	—	`conf`	A CMOS based operational floating current conveyor. ICECS Nermine M. Edward, Yehya H. Ghallab, Hassan M. Hassan, Yehea I. Ismail
2015	—	`conf`	A new digital locking MPPT control for ultra low power energy harvesting systems. NEWCAS Ayman Eltaliawy, Hassan Mostafa, Yehea I. Ismail
2015	C	`conf`	A tunable multi-band/multi-standard receiver front-end supporting LTE. ISCAS Hoda Abdelsalam, Emad Hegazi, Hassan Mostafa, Yehea I. Ismail
2015	—	`conf`	Coupling capacitance extraction in through-silicon via (TSV) arrays. ICECS Tarek Ramadan, Eslam Yahya, Mohamed Dessouky, Yehea I. Ismail
2015	C	`conf`	Design of adiabatic TSV, SWCNT TSV, and Air-Gap Coaxial TSV. ISCAS Khaled Salah, Yehea I. Ismail
2015	J	`jnl`	Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays. Microelectron. J. Karim Ali, Eslam Yahya, Alaa B. El-Rouby, Yehea I. Ismail
2015	J	`jnl`	Micro-scale variation-tolerant exponential tracking energy harvesting system for wireless sensor networks. Microelectron. J. Ayman Eltaliawy, Hassan Mostafa, Yehea I. Ismail
2015	—	`conf`	New TSV-Based applications: Resonant inductive coupling, variable inductor, power amplifier, bandpass filter, and antenna. NEWCAS Khaled Salah, Yehea I. Ismail
2015	—	`conf`	Performance evaluation of FinFET-based FPGA cluster under threshold voltage variation. NEWCAS Mohamed Mohie El-Din, Hassan Mostafa, Hossam A. H. Fahmy, Yehea I. Ismail, Hamdy Abdelhamid
2014	—	`conf`	A design oriented model for timing jitter/skew of Voltage-to-Time Converter (VTC) circuits. CCECE Hassan Mostafa, Yehea I. Ismail
2014	C	`conf`	A novel dimensional analysis method for TSV modeling and analysis in three dimensional integrated circuits. ISCAS Khaled Salah, Yehea I. Ismail
2014	C	`conf`	A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks. ISCAS Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail
2014	—	`conf`	Circuit design techniques for increasing the output power of switched capacitor charge pumps. CCECE Ayman Eltaliawy, Hassan Mostafa, Yehea I. Ismail
2014	J	`jnl`	Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip. IEEE Trans. Circuits Syst. I Regul. Pap. Wameedh Nazar Flayyih, Khairulmizam Samsudin, Shaiful J. Hashim, Fakhrul Zaman Rokhani, Yehea I. Ismail
2014	C	`conf`	Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks. ISCAS Abdelrahman H. Elsayed, Ramy N. Tadros, Maged Ghoneima, Yehea I. Ismail
2013	—	`conf`	A macro-modeling approach for through silicon via. EUROCON Khaled Salah, Hani F. Ragai, Yehea I. Ismail
2013	J	`jnl`	Editorial Appointments for the 2013-2014 Term. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail
2013	—	`conf`	Highly-linear voltage-to-time converter (VTC) circuit for time-based analog-to-digital converters (T-ADCs). ICECS Hassan Mostafa, Yehea I. Ismail
2013	—	`conf`	Microscale Solar Energy Harvesting for Wireless Sensor Networks based on Exponential Maximum power locking technique. ICECS Ayman Eltaliawy, Hassan Mostafa, Yehea I. Ismail
2013	—	`conf`	Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin
2013	C	`conf`	TSV-based on-chip inductive coupling communications. ISCAS Khaled Salah, Alaa B. El-Rouby, Hani F. Ragai, Yehea I. Ismail
2013	—	`conf`	Variability mitigation using correction function technique. ICECS Shady O. Agwa, Eslam Yahya, Yehea I. Ismail
2012	C	`conf`	A 16Gbps low power self-timed SerDes transceiver for multi-core communication. ISCAS Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail
2012	C	`conf`	A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. ISCAS Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail
2012	C	`conf`	A closed form expression for TSV-based on-chip spiral inductor. ISCAS Khaled Salah, Alaa B. El-Rouby, Hani F. Ragai, Yehea I. Ismail
2012	—	`conf`	A novel digital loop filter architecture for bang-bang ADPLL. SoCC Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdelsalam, Mohamed Abdel-Moneum, Nasser A. Kurd, Greg Taylor
2012	—	`conf`	Emitter-coupled spin-transistor logic. NANOARCH Joseph S. Friedman, Yehea I. Ismail, Gokhan Memik, Alan V. Sahakian, Bruce W. Wessels
2012	—	`conf`	InMnAs magnetoresistive spin-diode logic. ACM Great Lakes Symposium on VLSI Joseph S. Friedman, Nikhil Rangaraju, Yehea I. Ismail, Bruce W. Wessels
2012	—	`conf`	Modeling and analysis of through silicon via: Electromagnetic and device simulation approach. ICECS Khaled Salah, Alaa B. El-Rouby, Hani F. Ragai, Yehea I. Ismail
2012	—	`conf`	Modeling the response of Bang-Bang digital PLLs to phase error perturbations. CICC Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-Moneum, Nasser A. Kurd, Greg Taylor
2011	C	`conf`	A 12Gbps all digital low power SerDes transceiver for on-chip networking. ISCAS Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail
2011	C	`conf`	A Comprehensive Tapered buffer optimization algorithm for unified design metrics. ISCAS Song Liu, Seda Ogrenci Memik, Yehea I. Ismail
2011	J	`jnl`	A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahmed Shebaita, Debasish Das, Dusan Petranovic, Yehea I. Ismail
2011	—	`conf`	A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients. ICEAC Sally Safwat, Maged Ghoneima, Yehea I. Ismail
2011	C	`conf`	A dynamic calibration scheme for on-chip process and temperature variations. ISCAS Mina Raymond, Maged Ghoneima, Yehea I. Ismail
2011	—	`conf`	Body contact based TSV equalizer. IDT Khaled Mohamed, Alaa B. El-Rouby, Yehea I. Ismail, Hani F. Ragai
2011	C	`conf`	Compact lumped element model for TSV in 3D-ICs. ISCAS Khaled Salah, Alaa B. El-Rouby, Hani F. Ragai, Karim Amin, Yehea I. Ismail
2011	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail
2011	—	`conf`	Equivalent lumped element models for various n-port Through Silicon Vias networks. ASP-DAC Khaled Salah, Hani F. Ragai, Yehea I. Ismail, Alaa B. El-Rouby
2011	J	`jnl`	FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack
2011	C	`conf`	Fast hysteretic control of on-chip multi-phase switched-capacitor dc-dc converters. ISCAS Loai G. Salem, Yehea I. Ismail
2011	J	`jnl`	Floorplanning for low power IC design considering temperature variations. Microelectron. J. Kian Haghdad, Mohab Anis, Yehea I. Ismail
2011	—	`conf`	Low power FPAA design based on OTA using 90nm CMOS technology. ICEAC Soliman A. Mahmoud, Kareem Ali, Mahmoud Rabea, Abdallah Amgad, Ahmed Adel, Ahmed Nasser, Hussien Mohamed, Yehea I. Ismail
2011	—	`conf`	Resonant square-wave clock generator for low power applications. ICEAC Mohamed Wahba, Yehea I. Ismail
2011	—	`conf`	Slow-switching-limit loss removal in SC DC-DC converters using adiabatic charging. ICEAC Loai G. Salem, Yehea I. Ismail
2010	C	`conf`	A novel variation insensitive clock distribution methodology. ISCAS Ezz El-Din O. Hussein, Yehea I. Ismail
2010	J	`jnl`	SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation. IEEE Trans. Very Large Scale Integr. Syst. Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail
2009	J	`jnl`	A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Trans. Very Large Scale Integr. Syst. DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail
2009	J	`jnl`	SRAM dynamic stability estimation using MPFP and its applications. Microelectron. J. DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De
2009	J	`jnl`	SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2009	J	`jnl`	Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2009	J	`jnl`	Stable Parallelizable Model Order Reduction for Circuits With Frequency-Dependent Elements. IEEE Trans. Circuits Syst. I Regul. Pap. Shizhong Mei, Yehea I. Ismail
2008	—	`conf`	A global interconnect link design for many-core microprocessors. IFMT DiaaEldin Khalil, Yehea I. Ismail
2008	J	`jnl`	Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. Very Large Scale Integr. Syst. D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De
2008	C	`conf`	Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. ISCAS Sami Kirolos, Yehia Massoud, Yehea I. Ismail
2008	—	`conf`	Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De
2008	J	`jnl`	Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ja Chun Ku, Yehea I. Ismail
2008	—	`ch.`	Inductance Effects in Global Nets. Handbook of Algorithms for Physical Design Automation Yehea I. Ismail
2008	C	`conf`	Interconnect design and limitations in nanoscale technologies. ISCAS Yehea I. Ismail
2008	J	`jnl`	Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers. IEEE Trans. Circuits Syst. II Express Briefs Ahmed Shebaita, Yehea I. Ismail
2008	C	`conf`	Power-supply-variation-aware timing analysis of synchronous systems. ISCAS Sami Kirolos, Yehia Massoud, Yehea I. Ismail
2008	J	`jnl`	Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De
2007	C	`conf`	A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. ISCAS Ja Chun Ku, Yehea I. Ismail
2007	A	`conf`	A self-adjusting clock tree architecture to cope with temperature variations. ICCAD Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail
2007	J	`jnl`	An Accurate Low-Iteration Algorithm for Effective Capacitance Computation. J. Circuits Syst. Comput. Shizhong Mei, Yehea I. Ismail
2007	C	`conf`	Approximate Frequency Response Models for RLC Power Grids. ISCAS DiaaEldin Khalil, Yehea I. Ismail
2007	C	`conf`	Attaining Thermal Integrity in Nanometer Chips. ISCAS Ja Chun Ku, Yehea I. Ismail
2007	A	`conf`	Including inductance in static timing analysis. ICCAD Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail
2007	B	`conf`	Modeling and Characterizing Power Variability in Multicore Architectures. ISPASS Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail
2007	A	`conf`	Multi-layer interconnect performance corners for variation-aware timing analysis. ICCAD Frank Huebbers, Ali Dasdan, Yehea I. Ismail
2007	—	`conf`	NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. ACM Great Lakes Symposium on VLSI Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack
2007	J	`jnl`	On the Scaling of Temperature-Dependent Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ja Chun Ku, Yehea I. Ismail
2007	J	`jnl`	Thermal Management of On-Chip Caches Through Power Density Minimization. IEEE Trans. Very Large Scale Integr. Syst. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
2007	J	`jnl`	Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. IEEE Trans. Very Large Scale Integr. Syst. Ja Chun Ku, Yehea I. Ismail
2007	A	`conf`	Thermal-aware methodology for repeater insertion in low-power VLSI circuits. ISLPED Ja Chun Ku, Yehea I. Ismail
2007	C	`conf`	Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers. ISCAS Ahmed Shebaita, Yehea I. Ismail
2007	A	`conf`	Variable latency caches for nanoscale processor. SC Serkan Ozdemir, Arindam Mallik, Ja Chun Ku, Gokhan Memik, Yehea I. Ismail
2007	J	`jnl`	Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	A	`conf`	A timing dependent power estimation framework considering coupling. ICCAD Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
2006	—	`conf`	Area optimization for leakage reduction and thermal stability in nanometer scale technologies. ASP-DAC Ja Chun Ku, Yehea I. Ismail
2006	A*	`conf`	Computation of accurate interconnect process parameter values for performance corners under process variations. DAC Frank Huebbers, Ali Dasdan, Yehea I. Ismail
2006	C	`conf`	FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ICCD Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack
2006	J	`jnl`	Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2006	A	`conf`	Importance of volume discretization of single and coupled interconnects. ICCAD Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail
2006	C	`conf`	Optimum sizing of power grids for IR drop. ISCAS DiaaEldin Khalil, Yehea I. Ismail
2006	—	`conf`	Power density minimization for highly-associative caches in embedded processors. ACM Great Lakes Symposium on VLSI Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
2006	—	`ed.`	Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 ACM Great Lakes Symposium on VLSI Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou
2006	J	`jnl`	Realistic scalability of noise in dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. Masud H. Chowdhury, Yehea I. Ismail
2006	—	`conf`	Reducing the Data Switching Activity on Serial Link Buses. ISQED Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	J	`jnl`	Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2006	C	`conf`	Reducing the data switching activity of serialized datastreams. ISCAS Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	A	`conf`	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
2005	C	`conf`	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
2005	—	`conf`	Accurate decoupling of capacitively coupled buses. ISCAS (4) Maged Ghoneima, Yehea I. Ismail
2005	A	`conf`	Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. DSN Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
2005	A	`conf`	Expanding the frequency range of AWE via time shifting. ICCAD Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2005	—	`conf`	Low-power prediction based data transfer architecture. CICC Maged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea I. Ismail
2005	J	`jnl`	Optimum positioning of interleaved repeaters in bidirectional buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maged Ghoneima, Yehea I. Ismail
2005	—	`conf`	Physical limitations on the bit-rate of on-chip interconnects. ACM Great Lakes Symposium on VLSI Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail
2005	A*	`conf`	Piece-wise approximations of RLCK circuit responses using moment matching. DAC Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
2005	—	`ed.`	Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005 ACM Great Lakes Symposium on VLSI John C. Lach, Gang Qu, Yehea I. Ismail
2005	J	`jnl`	Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
2005	A	`conf`	Serial-link bus: a low-power on-chip bus architecture. ICCAD Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2005	—	`conf`	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
2005	A*	`conf`	Statistical static timing analysis: how simple can we get? DAC Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
2005	—	`conf`	The importance of including thermal effects in estimating the effectiveness of power reduction techniques. CICC Ja Chun Ku, Maged Ghoneima, Yehea I. Ismail
2005	A*	`conf`	Thermal Management of On-Chip Caches Through Power Density Minimization. MICRO Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
2005	J	`jnl`	Weibull-based analytical waveform model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2004	—	`conf`	Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]. CICC Masud H. Chowdhury, Yehea I. Ismail
2004	A	`conf`	Computation of signal threshold crossing times directly from higher order moments. ICCAD Yehea I. Ismail, Chirayu S. Amin
2004	J	`jnl`	Computation of signal-threshold crossing times directly from higher order moments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yehea I. Ismail, Chirayu S. Amin
2004	A	`conf`	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ISLPED Maged Ghoneima, Yehea I. Ismail
2004	—	`conf`	Effect of relative delay on the dissipated energy in coupled interconnects. ISCAS (2) Maged Ghoneima, Yehea I. Ismail
2004	A	`conf`	Formal derivation of optimal active shielding for low-power on-chip buses. ICCAD Maged Ghoneima, Yehea I. Ismail
2004	—	`conf`	Low power coupling-based encoding for on-chip buses. ISCAS (2) Maged Ghoneima, Yehea I. Ismail
2004	—	`conf`	Low-power on-chip bus architecture using dynamic relative delays. SoCC Maged Ghoneima, Yehea I. Ismail
2004	J	`jnl`	Modeling skin and proximity effects with reduced realizable RL circuits. IEEE Trans. Very Large Scale Integr. Syst. Shizhong Mei, Yehea I. Ismail
2004	A	`conf`	Modeling unbuffered latches for timing analysis. ICCAD Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2004	—	`conf`	Possible Noise Failure Modes in Static and Dynamic Circuits. IWSOC Masud H. Chowdhury, Yehea I. Ismail
2004	—	`conf`	Powder-based fabrication techniques for single-wall carbon nanotube circuits. ISCAS (3) Daniel Dai, Yehea I. Ismail, Wei Wang, Hanif M. Ladak
2004	J	`jnl`	Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. Maged Ghoneima, Yehea I. Ismail
2003	—	`conf`	Accurate rise time and overshoots estimation in RLC interconnects. ISCAS (5) Noha H. Mahmoud, Yehea I. Ismail
2003	—	`conf`	Analysis of Coupling Noise in Dynamic Circuit. IWSOC Masud H. Chowdhury, Yehea I. Ismail
2003	A*	`conf`	Efficient model order reduction including skin effect. DAC Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail
2003	J	`jnl`	Improved model-order reduction by using spacial information in moments. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail
2003	—	`conf`	Modeling skin effect with reduced decoupled R-L circuits. ISCAS (4) Shizhong Mei, Yehea I. Ismail
2003	J	`jnl`	On the Extraction of On-Chip Inductance. J. Circuits Syst. Comput. Yehea I. Ismail, Eby G. Friedman
2003	A*	`conf`	Optimum positioning of interleaved repeaters In bidirectional buses. DAC Maged Ghoneima, Yehea I. Ismail
2003	A*	`conf`	Realizable RLCK circuit crunching. DAC Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
2003	—	`conf`	Realizable reduction of RLC circuits using node elimination. ISCAS (3) Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
2003	A	`conf`	Weibull Based Analytical Waveform Model. ICCAD Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2002	J	`jnl`	DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yehea I. Ismail, Eby G. Friedman
2002	A	`conf`	Efficient model order reduction via multi-node moment matching. ICCAD Yehea I. Ismail
2002	—	`conf`	Evaluating noise pulses in RC networks due to capacitive coupling. ISCAS (5) Yehea I. Ismail
2002	J	`jnl`	Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail, Byron Krauter
2002	J	`jnl`	Inductance Effects in RLC Trees. J. Circuits Syst. Comput. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2002	J	`jnl`	On-chip inductance cons and pros. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail
2002	—	`conf`	Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
2001	J	`jnl`	Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2000	J	`jnl`	Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail, Eby G. Friedman
2000	J	`jnl`	Equivalent Elmore delay for RLC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2000	C	`conf`	Sensitivity of interconnect delay to on-chip inductance. ISCAS Yehea I. Ismail, Eby G. Friedman
1999	A*	`conf`	Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. DAC Yehea I. Ismail, Eby G. Friedman
1999	A*	`conf`	Equivalent Elmore Delay for DAC Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999	J	`jnl`	Figures of merit to characterize the importance of on-chip inductance. IEEE Trans. Very Large Scale Integr. Syst. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999	—	`conf`	Inductance Effects in RLC Trees. Great Lakes Symposium on VLSI Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999	—	`conf`	Repeater insertion in RLC lines for minimum propagation delay. ISCAS (6) Yehea I. Ismail, Eby G. Friedman
1999	A	`conf`	Repeater insertion in tree structured inductive interconnect. ICCAD Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999	—	`conf`	Signal waveform characterization in RLC trees. ISCAS (6) Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998	—	`conf`	Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. Great Lakes Symposium on VLSI Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998	A*	`conf`	Figures of Merit to Characterize the Importance of On-Chip Inductance. DAC Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998	A	`conf`	Power dissipated by CMOS gates driving lossless transmission lines. ISLPED Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998	—	`conf`	Transient power in CMOS gates driving LC transmission lines. ICECS Yehea I. Ismail, Eby G. Friedman, José Luis Neves