Yasuyuki Matsuya

13 papers Journal 13
YearRankTypeTitle / Venue / Authors
2021 J jnl
A Method for Detecting Timing of Photodiode Saturation without In-Pixel TDC for High-Dynamic-Range CMOS Image Sensor.
IEICE Trans. Electron.
Yuji Inagaki, Yasuyuki Matsuya
2017 J jnl
A Logarithmic Compression ADC Using Transient Response of a Comparator.
IEICE Trans. Electron.
Yuji Inagaki, Yusaku Sugimori, Eri Ioka, Yasuyuki Matsuya
2016 J jnl
Noise Characteristic of the Chaotic Double Loop Delta Sigma Modulator.
Int. J. Bifurc. Chaos
Eri Ioka, Nozomi Watanabe, Ryo Makishima, Yasuyuki Matsuya
2015 J jnl
Causal analysis between vehicle operating data and physiological responses.
Artif. Life Robotics
Shizuka Bando, Akio Nozawa, Yasuyuki Matsuya
2011 J jnl
FOREWORD.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuyuki Matsuya
2009 J jnl
A Stereo Transmission Technique Using PDM Data and Synchronized Clock Channels.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuyuki Matsuya, Takahiro Mesuda
2005 J jnl
A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks.
IEICE Trans. Electron.
Jun Terada, Yasuyuki Matsuya, Shin'ichiro Mutoh, Yuichi Kado
2003 J jnl
8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jun Terada, Yasuyuki Matsuya, Fumiharu Morisawa, Yuichi Kado
1997 J jnl
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits.
IEEE J. Solid State Circuits
Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada
1996 J jnl
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application.
IEEE J. Solid State Circuits
Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada
1995 J jnl
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS.
IEEE J. Solid State Circuits
Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada
1994 J jnl
1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping.
IEEE J. Solid State Circuits
Yasuyuki Matsuya, Junzo Yamada
1989 J jnl
A 17 bit oversampling D-A conversion technology using multistage noise shaping.
IEEE J. Solid State Circuits
Yasuyuki Matsuya, Kuniharu Uchimura, Atsushi Iwata, Takao Kaneko