Yasuto Kuroda

19 papers B 1C 2Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2016 J jnl
Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching.
Photonic Netw. Commun.
Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Yuji Yano, Shoji Koyama
2016 — conf
Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure.
CCNC
Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka
2015 — conf
Demonstrating 100 Gbps optical packet switching using 16-bit longest prefix matching forwarding engine.
ONDM
Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama
2014 — conf
Development of onboard LPM-based header processing and reactive link selection for optical packet and circuit integrated networks.
ICC
Hideaki Furukawa, Takaya Miyazawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama, Shin'ichi Arakawa, Masayuki Murata
2013 — conf
2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving.
CCNC
Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka
2013 J jnl
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application.
IEICE Trans. Electron.
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka
2013 J jnl
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS.
IEEE J. Solid State Circuits
Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai
2013 J jnl
A study on micro level traffic prediction for energy-aware routers.
ACM SIGOPS Oper. Syst. Rev.
Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka
2013 J jnl
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS.
IEICE Trans. Commun.
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue
2012 — conf
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application.
CICC
Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki
2012 C conf
A slice structure using the management of network traffic prediction for green IT.
HPSR
Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue
2012 B conf
Deterministic High Density Packet-Buffer System for Low Cost Network Systems.
AINA
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue
2012 J jnl
FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine.
IEICE Trans. Commun.
Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka
2010 — conf
Hardware implementation of fast forwarding engine using standard memory and dedicated circuit.
ICECS
Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka
2008 J jnl
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
IEICE Trans. Electron.
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007 J jnl
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.
IEICE Trans. Inf. Syst.
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007 C conf
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.
ISCAS
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007 J jnl
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.
IEICE Trans. Inf. Syst.
Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2005 — conf
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].
ISCAS (5)
Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito