Yasutaka Wada

36 papers A 1B 1C 2Misc 1Journal 17Unranked 14
YearRankTypeTitle / Venue / Authors
2025 J jnl
Enabling Dynamic Approximate Computing for HPC Applications.
J. Inf. Process.
Yasutaka Wada, Yoshiyuki Morie, Ryohei Kobayashi, Ryuichi Sakamoto
2025 J jnl
Foreword.
IEICE Trans. Electron.
Ryusuke Egawa, Yasutaka Wada
2025 J jnl
Special Issue on COOL Chips.
IEEE Micro
Ryusuke Egawa, Yasutaka Wada
2024 J jnl
Foreword.
IEICE Trans. Electron.
Ryusuke Egawa, Yasutaka Wada
2024 Misc conf
Ideal Parametrisation Estimation for Variational Quantum Circuit Classifiers Using Machine Learning.
QCE
Mostafa Fathi, Walid Gomaa, Yasutaka Wada, Keiji Kimura, Kazunori Ueda, Ahmed El-Mahdy
2024 J jnl
Special Issue on COOL Chips.
IEEE Micro
Ryusuke Egawa, Yasutaka Wada
2023 J jnl
Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems.
Int. J. Netw. Comput.
Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto
2023 J jnl
Foreword.
IEICE Trans. Electron.
Ryusuke Egawa, Yasutaka Wada
2023 J jnl
Special Issue on Cool Chips.
IEEE Micro
Ryusuke Egawa, Yasutaka Wada
2022 — conf
Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems.
IPDPS Workshops
Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto
2021 — conf
An FPGA-Based Image Recognition with Remote Update Functions for Autonomous Driving on "ad-refkit".
FPT
Hyuga Hashimoto, Ryo Naka, Yasutaka Wada
2021 J jnl
Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems.
IEICE Trans. Electron.
Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Guanqin Pan, Thang Cao, Masaaki Kondo
2021 — conf
Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL.
CANDAR (Workshops)
Yunjiao Ma, Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Masaaki Kondo
2021 J jnl
Secure Image Inference Using Pairwise Activation Functions.
IEEE Access
Jonas T. Agyepong, Mostafa Soliman, Yasutaka Wada, Keiji Kimura, Ahmed El-Mahdy
2019 — conf
Towards the Improvement of Training Efficiency and Image Recognition Accuracy for an FPGA Controlled Mini-Car by Offloading Neural Network Training.
FPT
Musashi Aoto, Moe Mitsugi, Takumi Momose, Yasutaka Wada
2018 — conf
A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems.
SCFA
Yasutaka Wada, Yuan He, Thang Cao, Masaaki Kondo
2018 — conf
Development of an FPGA Controlled "Mini-Car" Toward Autonomous Driving.
FPT
Musashi Aoto, Yasutaka Wada, Yousuke Numata
2015 J jnl
A Linear Time and Space Algorithm for Optimal Traffic-Signal Duration at an Intersection.
IEEE Trans. Intell. Transp. Syst.
Sameh Samra, Ahmed El-Mahdy, Yasutaka Wada
2015 A conf
Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing.
SC
Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David K. Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, Ikuo Miyoshi
2015 — conf
Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers.
LCPC
Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2015 J jnl
Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier.
IEEE Embed. Syst. Lett.
Ghada Y. Abozaid, Arnaud Tisserand, Ahmed El-Mahdy, Yasutaka Wada
2013 J jnl
A Linear-Time and Space Algorithm for Optimal Traffic Signal Durations at an Intersection.
CoRR
Sameh Samra, Ahmed El-Mahdy, Yasutaka Wada
2013 C conf
A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption.
DSD
Ghada Y. Abozaid, Ahmed El-Mahdy, Yasutaka Wada
2011 J jnl
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron.
Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
2011 J jnl
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.
Trans. High Perform. Embed. Archit. Compil.
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
2011 — conf
Efficient Parallel Implementations of Controlled Optimization of Traffic Phases.
ICA3PP (1)
Sameh Samra, Ahmed El-Mahdy, Walid Gomaa, Yasutaka Wada, Amin A. Shoukry
2010 — conf
A 45nm 37.3GOPS/W heterogeneous multi-core SoC.
ISSCC
Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
2010 — conf
Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores.
LCPC
Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara
2008 J jnl
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.
IEEE J. Solid State Circuits
Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2008 C conf
Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API.
ISPA
Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
2008 J jnl
Power-Aware Compiler Controllable Chip Multiprocessor.
IEICE Trans. Electron.
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2008 — conf
Software-cooperative power-efficient heterogeneous multi-core for media processing.
ASP-DAC
Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2007 B conf
Power-Aware Compiler Controllable Chip Multiprocessor.
PACT
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2005 — conf
Compiler Control Power Saving Scheme for Multi Core Processors.
LCPC
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
2005 — conf
Multigrain parallel processing on compiler cooperative chip multiprocessor.
Interaction between Compilers and Computer Architectures
Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara
2005 — conf
Performance Evaluation of Compiler Controlled Power Saving Scheme.
ISHPC
Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara