Yasushi Yuminaka

49 papers B 2Journal 18Unranked 29
YearRankTypeTitle / Venue / Authors
2025 J jnl
Analog VLSI Implementation of Subthreshold Spiking Neural Networks and Its Application to Reservoir Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Satoshi Moriya, Masaya Ishikawa, Satoshi Ono, Hideaki Yamamoto, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
2025 — conf
Multi-Valued Data Transmission System Using Mild Waveform Shaping Based on Multi-Dimensional Symbol Mapping.
ISMVL
Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka
2025 — conf
Visualization of the Waveform Shaping Effect of Higher-order FFEs Using Multi-Valued Symbol Mapping.
ISMVL
Yasushi Yuminaka, Ryou Andachi, Haohao Zhang, Yosuke Iijima
2024 B conf
Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing.
IJCNN
Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
2024 — conf
Equalization for Compensation of Intersymbol Relationship of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping.
ISMVL
Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka
2024 J jnl
Evaluating PAM-4 Data Transmission Quality Using Multi-Dimensional Mapping of Received Symbols.
IEICE Trans. Inf. Syst.
Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima
2024 J jnl
Evaluation of Multi-Valued Data Transmission in Two-Dimensional Symbol Mapping using Linear Mixture Model.
IEICE Trans. Inf. Syst.
Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka
2024 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Yasushi Yuminaka
2024 — conf
Specialized Waveform Equalization Techniques for Multi-Valued Data Transmission.
ISMVL
Yasushi Yuminaka, Hayate Hasegawa, Nagito Ishida, Yosuke Iijima
2023 — conf
Evaluation and Symbol Classification of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping with Linear Mixture Model.
ISMVL
Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka
2023 J jnl
Multi-Valued Data Transmission Quality Evaluation Using Two-Dimensional PAM-4 Symbol Mapping.
FLAP
Kazuharu Nakajima, Yasushi Yuminaka, Yosuke Iijima
2023 — conf
PAM-4 Data Transmission Quality Evaluation Using Two- and Three-Dimensional Mapping of Received Symbols.
ISMVL
Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima
2022 B conf
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation.
IJCNN
Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas
2022 J jnl
Efficient PAM-4 Symbol Estimation Using Soft Clustering.
FLAP
Yosuke Iijima, Yasushi Yuminaka
2022 — conf
Two-Dimensional Symbol Mapping for Evaluating Multi-Valued Data Transmission Quality.
ISMVL
Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka
2021 — conf
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model.
ICANN (5)
Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas
2021 — conf
Efficient PAM-4 Data Transmission with Closed Eye Using Symbol Distribution Estimation.
ISMVL
Yosuke Iijima, Yasushi Yuminaka
2021 J jnl
PAM-4 Eye-Opening Monitor Technique Using Gaussian Mixture Model for Adaptive Equalization.
IEICE Trans. Inf. Syst.
Yosuke Iijima, Keigo Taya, Yasushi Yuminaka
2020 — conf
PAM-4 Eye-Opening Monitoring Techniques Using Gaussian Mixture Model.
ISMVL
Yosuke Iijima, Keigo Taya, Yasushi Yuminaka
2020 J jnl
PAM-4 Signal Transmitter using FPGA and DAC for Serial-link Test.
FLAP
Yasushi Yuminaka, Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima
2020 J jnl
Statistical Waveform Evaluation Method for Adaptive PAM-4 Equalization.
FLAP
Keigo Taya, Yasushi Yuminaka, Yosuke Iijama
2019 — conf
Waveform Shaping Transmitter Combining Digital and Analog Circuits for Multi - Valued Signaling.
ISMVL
Yosuke Iijima, Yasushi Yuminaka
2018 — conf
Multi-valued Signal Generation and Measurement for PAM-4 Serial-Link Test.
ISMVL
Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima, Yasushi Yuminaka
2017 J jnl
Double-Rate Tomlinson-Harashima Precoding for Multi-Valued Data Transmission.
IEICE Trans. Inf. Syst.
Yosuke Iijima, Yasushi Yuminaka
2017 — conf
PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-valued Data Transmissions.
ISMVL
Yasushi Yuminaka, Takuya Kitamura, Yosuke Iijima
2016 J jnl
Comparison of Spectrally Efficient Coding Techniques for High-Speed VLSI Data Transmission.
J. Multiple Valued Log. Soft Comput.
Yasushi Yuminaka, Yuuki Takada, Tomonao Okada
2016 — conf
Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-valued Data Transmission.
ISMVL
Yosuke Iijima, Yasushi Yuminaka
2016 J jnl
Multiple-Valued Signaling for High-Speed Serial Links Using Tomlinson-Harashima Precoding.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yasushi Yuminaka, Yosuke Iijima
2014 — conf
Comparison of Spectrally Efficient Coding Techniques for High-Speed Serial Links.
ISMVL
Yasushi Yuminaka, Yuki Takada, Tomonao Okada, Yosuke Iijima
2014 — conf
Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding.
ISMVL
Yosuke Iijima, Yasushi Yuminaka
2014 J jnl
High-Speed Interconnection for VLSI Systems Using Multiple-Valued Signaling with Tomlinson-Harashima Precoding.
IEICE Trans. Inf. Syst.
Yosuke Iijima, Yuki Takada, Yasushi Yuminaka
2012 J jnl
A Bandwidth-Efficient Ternary Signaling Scheme for 1-D Partial-Response Channels.
J. Multiple Valued Log. Soft Comput.
Yasushi Yuminaka, Kyohei Kawano
2012 — conf
Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation.
ISMVL
Yasushi Yuminaka, Masaaki Okui
2010 — conf
A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface.
ISMVL
Yasushi Yuminaka, Kyohei Kawano
2010 J jnl
Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques.
IEICE Trans. Inf. Syst.
Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi
2009 — conf
Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects.
ISMVL
Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi
2009 J jnl
Time-Domain Pre-Emphasis Techniques for Multiple Valued Data Transmission.
J. Multiple Valued Log. Soft Comput.
Yasushi Yuminaka, Yasunori Takahashi
2008 — conf
Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data.
ISMVL
Yasushi Yuminaka, Yasunori Takahashi
2007 — conf
Equalization Techniques for Multiple-Valued Data Transmission and Their Application.
ISMVL
Yasushi Yuminaka, Kazuyoshi Yamamura
2007 J jnl
Equalization Techniques for Multiple-Valued Data Transmission and Their Application.
J. Multiple Valued Log. Soft Comput.
Yasushi Yuminaka, Kazuyoshi Yamamura
2005 J jnl
Intra/Inter-Chip CDMA Communications for Efficient Data Transmission Towards New Paradigm of Computing.
J. Multiple Valued Log. Soft Comput.
Yasushi Yuminaka
2002 — conf
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI.
ISMVL
Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi
2000 — conf
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access.
ISMVL
Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
1999 — conf
A high-speed CMOS track/hold circuit.
ICECS
Mohd Asmawi Mohamed Zin, Haruo Kobayashi, Kazuya Kobayashi, Jun-ichi Ichimura, Hao San, Yoshitaka Onaya, Yasuyuki Kimura, Yasushi Yuminaka, Yoshisato Sasaki, Kouji Tanaka, Fuminori Abe
1998 — conf
Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences.
ISMVL
Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
1996 — conf
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves.
ISMVL
Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi
1994 — conf
Design of Wave-Parallel Computing Circuits for Densely Connected Architectures.
ISMVL
Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
1993 — conf
Design of Set-Valued Logic Networks for Wave-Parallel Computing.
ISMVL
Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
1991 — conf
Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing.
ISMVL
Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi