Yasuo Takahashi

13 papers C 1Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2017 C conf
Associative search using pseudo-analog memristors.
ISCAS
Mika Laiho, Mika Grönroos, Jussi H. Poikonen, Eero Lehtonen, Reon Katsumura, Atsushi T.-Fukuchi, Masashi Arita, Yasuo Takahashi
2016 J jnl
Brownian Circuits: Designs.
Int. J. Unconv. Comput.
Jia Lee, Ferdinand Peper, Sorin Dan Cotofana, Makoto Naruse, Motoichi Ohtsu, Tadashi Kawazoe, Yasuo Takahashi, Tetsuya Shimokawa, Laszlo B. Kish, Tohru Kubota
2012 J jnl
Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device.
IEICE Trans. Electron.
Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi
2011 J jnl
Anomalous microstructure formed at the interface between copper ribbon and tin-deposited copper plate by ultrasonic bonding.
Microelectron. Reliab.
Masakatsu Maeda, Takaaki Sato, Naoto Inoue, Daisuke Yagi, Yasuo Takahashi
2009 J jnl
Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs.
Int. J. Nanotechnol. Mol. Comput.
Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi
2007 J jnl
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.
J. Multiple Valued Log. Soft Comput.
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2007 J jnl
Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors.
IEICE Trans. Electron.
Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu
2006 — conf
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
2005 — conf
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
2004 — conf
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2004 — conf
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
ISMVL
Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2003 — conf
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic.
ISMVL
Hiroshi Inokawa, Yasuo Takahashi
2000 — conf
Silicon Single-Electron Devices and Their Applications.
ISMVL
Yasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase