Yasuo Sato - RankMe

66 papers A* 2A 9B 5C 3Misc 6Journal 14Unranked 27

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
2020	J	`jnl`	Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gian Mayuga, Yasuo Sato, Michiko Inoue
2019	—	`conf`	A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. ITC-Asia Yousuke Miyake, Yasuo Sato, Seiji Kajihara
2019	C	`conf`	On-Chip Delay Measurement for In-Field Test of FPGAs. PRDC Yousuke Miyake, Yasuo Sato, Seiji Kajihara
2018	—	`conf`	Good Die Prediction Modelling from Limited Test Items. ITC-Asia Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura
2018	—	`conf`	On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara
2017	—	`conf`	On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. ITC-Asia Yousuke Miyake, Yasuo Sato, Seiji Kajihara
2016	—	`conf`	A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
2016	B	`conf`	Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
2016	J	`jnl`	Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
2016	J	`jnl`	Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
2015	B	`conf`	An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato
2015	J	`jnl`	Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi
2014	—	`conf`	An On-Chip Digital Environment Monitor for Field Test. ATS Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura
2014	J	`jnl`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2014	C	`conf`	Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA. PRDC Yasuo Sato, Masafumi Monden, Yousuke Miyake, Seiji Kajihara
2014	—	`conf`	Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
2013	—	`conf`	A Stochastic Model for NBTI-Induced LSI Degradation in Field. Asian Test Symposium Yasuo Sato, Seiji Kajihara
2013	—	`conf`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2013	J	`jnl`	Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase
2012	J	`jnl`	A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2012	—	`conf`	A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara
2012	A	`conf`	DART: Dependable VLSI test architecture and its implementation. ITC Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
2012	—	`conf`	Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara
2012	B	`conf`	On-chip temperature and voltage measurement for field testing. ETS Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara
2011	—	`conf`	Genetic algorithm based approach for segmented testing. DSN Workshops Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato
2011	—	`conf`	Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. Asian Test Symposium Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara
2011	Misc	`conf`	Special session: Multifaceted approaches for field reliability. VTS Yasuo Sato
2011	B	`conf`	Temperature-Variation-Aware Test Pattern Optimization. ETS Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
2010	C	`conf`	Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2010	—	`conf`	Circuit Failure Prediction by Field Test - A New Task of Testing. DFT Yasuo Sato
2010	J	`jnl`	On Delay Test Quality for Test Cubes. Inf. Media Technol. Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
2010	J	`jnl`	On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
2010	B	`conf`	On estimation of NBTI-Induced delay degradation. ETS Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
2010	Misc	`conf`	Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
2008	J	`jnl`	Post-BIST Fault Diagnosis for Multiple Faults. IEICE Trans. Inf. Syst. Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
2007	—	`conf`	Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian
2006	A	`conf`	A Framework of High-quality Transition Fault ATPG for Scan Circuits. ITC Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006	J	`jnl`	A Statistical Quality Model for Delay Testing. IEICE Trans. Electron. Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
2006	—	`conf`	A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006	—	`conf`	At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo
2006	—	`conf`	Defect Diagnosis - Reasoning Methodology. ATS Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, Masaru Sanada
2006	—	`conf`	Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
2006	—	`conf`	Not all Delay Tests Are the Same - SDQL Model Shows True-Time. ATS Anis Uzzaman, Mick Tegethoff, Bibo Li, Kevin McCauley, Shuji Hamada, Yasuo Sato
2006	A	`conf`	Recognition of Sensitized Longest Paths in Transition Delay Test. ITC Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Noduyama, Yasuo Sato
2006	—	`conf`	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
2005	—	`conf`	Evaluation of the statistical delay quality model. ASP-DAC Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
2005	A	`conf`	Invisible delay quality - SDQM model lights up what could not be seen. ITC Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara
2005	A*	`conf`	Path delay test compaction with process variation tolerance. DAC Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2004	J	`jnl`	Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki
2003	J	`jnl`	DFT Timing Design Methodology for Logic BIST. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Kazumi Hatayama, Kazuyuki Nomoto
2003	—	`conf`	DFT timing design methodology for at-speed BIST. ASP-DAC Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto
2002	A	`conf`	A Persistent Diagnostic Technique for Unstable Defects. ITC Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura
2002	A	`conf`	Application of High-Quality Built-In Test to Industrial Designs. ITC Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
2002	—	`conf`	At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
2001	—	`conf`	A Practical Logic BIST for ASIC Designs. Asian Test Symposium Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Toyohito Ikeya, Masatoshi Kawashima
2001	—	`conf`	An Approach to Improve the Resolution of Defect-Based Diagnosis. Asian Test Symposium Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato
2001	A	`conf`	An evaluation of defect-oriented test: WELL-controlled low voltage test. ITC Yasuo Sato, Masaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto
2001	—	`conf`	Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
2000	A	`conf`	A BIST approach for very deep sub-micron (VDSM) defects. ITC Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo
1996	A	`conf`	A Snapshot Algorithm for Distributed Mobile Systems. ICDCS Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1991	A*	`conf`	Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. DAC Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima
1986	Misc	`conf`	Connected word recognition by overlap and split of reference patterns and its performance evaluation tests. ICASSP Koji Tajima, Mitsuo Komura, Yasuo Sato
1984	Misc	`conf`	Automatic recognition of spoken words from a large vocabulary using syllable templates. ICASSP Hiroya Fujisaki, Keikichi Hirose, Tomohiro Inoue, Yasuo Sato
1984	Misc	`conf`	Spectral envelope sampling and interpolation in linear predictive analysis of speech. ICASSP Hynek Hermansky, Hiroya Fujisaki, Yasuo Sato
1983	Misc	`conf`	Analysis and synthesis of speech based on spectral transform linear predictive method. ICASSP Hynek Hermansky, Hiroya Fujisaki, Yasuo Sato