Yasuo Itoh - RankMe

16 papers B 2Misc 1Journal 13

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving. IEEE J. Solid State Circuits Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka
2008	B	`conf`	Is the perceived agreeability of a face related to the fractal dimension of the face? SMC Yasuo Itoh, Mayumi Oyama-Higa, Tiejun Miao
2008	J	`jnl`	Relationship between fractal dimension and favorability of facial imagery. Int. J. Hybrid Intell. Syst. Mayumi Oyama-Higa, Tiejun Miao, Yasuo Itoh
2007	B	`conf`	Does the transition of the interval in perceptional alternation have a chaotic rhythm? SMC Yasuo Itoh, Mayumi Oyama
2006	J	`jnl`	Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada
2001	J	`jnl`	A 76-mm IEEE J. Solid State Circuits Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki
2000	J	`jnl`	A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. IEEE J. Solid State Circuits Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka
1997	J	`jnl`	A 120-mm IEEE J. Solid State Circuits Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto
1995	J	`jnl`	A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. IEEE J. Solid State Circuits Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto
1991	J	`jnl`	A 4 Mb NAND EEPROM with tight programmed V IEEE J. Solid State Circuits Masaki Momodomi, Tomoharu Tanaka, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka
1990	J	`jnl`	A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. IEEE J. Solid State Circuits Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka
1990	J	`jnl`	A high-density NAND EEPROM with block-page programming for microcomputer applications. IEEE J. Solid State Circuits Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka
1989	J	`jnl`	An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka
1989	J	`jnl`	An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. IEEE J. Solid State Circuits Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka
1989	J	`jnl`	New nibbled-page architecture for high-density DRAMs. IEEE J. Solid State Circuits Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi
1983	Misc	`conf`	An adaptive echo canceller using digital signal processor LSI chips. ICASSP Kazunori Ozawa, Takashi Araseki, Yasuo Itoh