Yasuo Hidaka

13 papers A* 1Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2013 — conf
32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE.
ISSCC
Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura
2013 — conf
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS.
ISSCC
Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada
2013 J jnl
Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters.
IEEE J. Solid State Circuits
Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon
2012 — conf
A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS.
CICC
Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon
2011 — conf
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.
ISSCC
Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker
2009 J jnl
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control.
IEEE J. Solid State Circuits
Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
2009 — conf
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control.
ISSCC
Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
2007 — conf
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.
ISSCC
Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone
2007 — conf
Design Consideration of 6.25 Gbps Signaling for High-Performance Server.
ASP-DAC
Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone
1994 J jnl
Architecture of parallel management kernel for PIE64.
Future Gener. Comput. Syst.
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
1993 A* conf
Multiple Threads in Cyclic Register Windows.
ISCA
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
1992 — conf
Architecture of Parallel Management Kernel for PIE64.
PARLE
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
1991 — conf
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages.
ISLP
Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka