Yasunobu Nakase

17 papers C 1Journal 12Unranked 4

Year	Rank	Type	Title / Venue / Authors
2014	—	`conf`	A low power NoC router using the marching memory through type. COOL Chips Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014	—	`conf`	Design of a low power NoC router using Marching Memory Through type. NOCS Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2013	J	`jnl`	0.5 V Start-Up 87% Efficiency 0.75 mm IEEE J. Solid State Circuits Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu
2013	J	`jnl`	On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes. IEICE Trans. Electron. Yasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, Toru Shimizu
2012	—	`conf`	A 0.5V start-up 87% efficiency 0.75mm CICC Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu
2011	—	`conf`	0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. A-SSCC Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu
2001	J	`jnl`	A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba
1999	J	`jnl`	Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
1997	J	`jnl`	Authors Reply. IEEE J. Solid State Circuits Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko
1997	J	`jnl`	Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1996	J	`jnl`	A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1996	J	`jnl`	An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
1996	J	`jnl`	Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1995	J	`jnl`	A BiCMOS wired-OR logic. IEEE J. Solid State Circuits Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
1993	C	`conf`	A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. ICCD Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
1991	J	`jnl`	A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. IEEE J. Solid State Circuits Yasunobu Nakase, Kakutaro Suda, Koichiro Mashiko, Tatsuhiko Ikeda, Shinpei Kayano
1988	J	`jnl`	A macro analysis of soft errors in static RAMs. IEEE J. Solid State Circuits Yasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano