Yasunao Katayama

37 papers A* 2A 4B 7C 2Journal 6Unranked 16

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Spatially Arranged Sparse Recurrent Neural Networks for Energy Efficient Associative Memory. IEEE Trans. Neural Networks Learn. Syst. Gouhei Tanaka, Ryosho Nakane, Tomoya Takeuchi, Toshiyuki Yamane, Daiju Nakano, Yasunao Katayama, Akira Hirose
2019	B	`conf`	Channel Model for Spiking Neural Networks Inspired by Impulse Radio MIMO Transmission. GLOBECOM Yasunao Katayama
2019	J	`jnl`	Like Quantum Computing without Quantum Physics: Is it How the Brain Works? CoRR Yasunao Katayama
2017	—	`conf`	Brain-Inspired Memory Architecture for Sparse Nonlocal and Unstructured Workloads. Conf. Computing Frontiers Yasunao Katayama
2015	B	`conf`	Regularity and randomness in modular network structures for neural associative memories. IJCNN Gouhei Tanaka, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Yasunao Katayama
2015	—	`conf`	Single-channel full-duplex mmWave link using phased-array for Ethernet. CCNC Yasuteru Kohda, Kohji Takano, Daiju Nakano, Nobuyuki Ohba, Toshiyuki Yamane, Yasunao Katayama
2015	—	`conf`	Wave-Based Reservoir Computing by Synchronization of Coupled Oscillators. ICONIP (3) Toshiyuki Yamane, Yasunao Katayama, Ryosho Nakane, Gouhei Tanaka, Daiju Nakano
2015	—	`conf`	Wave-based device scaling concept for brain-like energy efficiency and integration. NANOARCH Yasunao Katayama, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Gouhei Tanaka
2014	B	`conf`	60-GHz single-carrier coherent detection system with robust 16-QAM signal recovery. WCNC Daiju Nakano, Yasuteru Kohda, Kohji Takano, Nobuyuki Ohba, Toshiyuki Yamane, Yasunao Katayama
2014	—	`conf`	An Energy-Efficient Computing Approach by Filling the Connectome Gap. UCNC Yasunao Katayama, Toshiyuki Yamane, Daiju Nakano
2014	—	`conf`	Hopfield-Type Associative Memory with Sparse Modular Networks. ICONIP (1) Gouhei Tanaka, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Yasunao Katayama
2014	—	`conf`	Non-intrusive Scalable Memory Access Tracer. QEST Nobuyuki Ohba, Seiji Munetoh, Atsuya Okazaki, Yasunao Katayama
2013	—	`conf`	Software-defined massive multicore networking via freespace optical interconnect. Conf. Computing Frontiers Yasunao Katayama, Atsuya Okazaki, Nobuyuki Ohba
2012	B	`conf`	An effective initialization of interference cancellation algorithms for distributed MIMO systems in wireless datacenters. GLOBECOM Toshiyuki Yamane, Yasunao Katayama
2012	B	`conf`	MIMO link design strategy for wireless data center applications. WCNC Yasunao Katayama, Toshiyuki Yamane, Yasuteru Kohda, Kohji Takano, Daiju Nakano, Nobuyuki Ohba
2012	—	`conf`	Multimedia content-downloading system using millimeter-wave attached memory. CCNC Nobuyuki Ohba, Kohji Takano, Yasuteru Kohda, Daiju Nakano, Toshiyuki Yamane, Yasunao Katayama
2011	A	`conf`	Instant multimedia contents downloading system using a 60-GHZ-2.4-GHZ hybrid wireless link. ICME Yasuteru Kohda, Nobuyuki Ohba, Kohji Takano, Daiju Nakano, Toshiyuki Yamane, Yasunao Katayama
2011	—	`conf`	Multi-Gbps 60-GHz single-carrier system using a low-power coherent detection technique. COOL Chips Daiju Nakano, Yasuteru Kohda, Kohji Takano, Toshiyuki Yamane, Nobuyuki Ohba, Yasunao Katayama
2011	—	`conf`	Universal optical multi-drop bus for heterogeneous memory architecture. Conf. Computing Frontiers Atsuya Okazaki, Yasunao Katayama, Seiji Munetoh
2011	B	`conf`	Wireless data center networking with steered-beam mmWave links. WCNC Yasunao Katayama, Kohji Takano, Yasuteru Kohda, Nobuyuki Ohba, Daiju Nakano
2008	A	`conf`	Multi-Gbps wireless systems over 60-GHz SiGe radio link with BW-efficient noncoherent detections. ICME Yasunao Katayama, Daiju Nakano, Alberto Valdes-Garcia, Troy J. Beukema, Scott K. Reynolds
2007	—	`conf`	2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link. CCNC Yasunao Katayama, Chuck Haymes, Daiju Nakano, Troy J. Beukema, Brian A. Floyd, Scott K. Reynolds, Ullrich R. Pfeiffer, Brian P. Gaucher, Kai Schleupen
2007	A*	`conf`	Optical Interconnect Opportunities for Future Server Memory Systems. HPCA Yasunao Katayama, Atsuya Okazaki
2006	B	`conf`	Multiple-Packet Recovery Technique using Partially-Overlapped Block Codes. ISIT Yasunao Katayama, Daiju Nakano
2003	—	`conf`	An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability. ICASSP (2) Toshiyuki Yamane, Yasunao Katayama
2003	A	`conf`	An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability. ICME Toshiyuki Yamane, Yasunao Katayama
2003	—	`conf`	Bit error rate analysis on iterative two-stage decoding of two dimensional codes by importance sampling. ICC Toshiyuki Yamane, Yasunao Katayama
2001	A*	`conf`	Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2 CAV Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane
2000	—	`conf`	Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. DFT Yasunao Katayama, Yasushi Negishi, Sumio Morioka
2000	A	`conf`	One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems. DSN Yasunao Katayama, Sumio Morioka
1999	C	`conf`	Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. ICCD Sumio Morioka, Yasunao Katayama
1999	—	`conf`	Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. DFT Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu
1997	C	`conf`	Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
1997	J	`jnl`	Trends in semiconductor memories. IEEE Micro Yasunao Katayama
1992	J	`jnl`	A 14-ns 14-Mb CMOS DRAM with 300-mW active power. IEEE J. Solid State Circuits Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa
1992	J	`jnl`	A pulsed sensing scheme with a limited bit-line swing. IEEE J. Solid State Circuits Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong
1989	J	`jnl`	A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. IEEE J. Solid State Circuits Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano