Yasumoto Tomita

23 papers A 2B 1Journal 8Unranked 12

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Acceleration of Structural Analysis Simulations using CNN-based Auto-Tuning of Solver Tolerance. IPDPS Workshops Amir Haderbache, Koichi Shirahata, Takuji Yamamoto, Yasumoto Tomita, Hiroshi Okuda
2018	J	`jnl`	An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. IEEE J. Solid State Circuits Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita
2018	J	`jnl`	GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning. Int. J. Netw. Comput. Koichi Shirahata, Youri Coppens, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike
2018	B	`conf`	Speed-Up of Object Detection Neural Network with GPU. ICIP Takuya Fukagai, Kyosuke Maeda, Satoshi Tanabe, Koichi Shirahata, Yasumoto Tomita, Atsushi Ike, Akira Nakagawa
2017	A	`conf`	An automated CNN recommendation system for image classification tasks. ICME Song Wang, Li Sun, Wei Fan, Jun Sun, Satoshi Naoi, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike, Tetsutaro Hashimoto
2017	—	`conf`	GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning. CANDAR Youri Coppens, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike
2016	J	`jnl`	An Automated CNN Recommendation System for Image Classification Tasks. CoRR Song Wang, Li Sun, Wei Fan, Jun Sun, Satoshi Naoi, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike
2016	A	`conf`	An FPGA-accelerated partial duplicate image retrieval engine for a document search system. WACV Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, Yasumoto Tomita, Takayuki Baba, Yasuhiro Watanabe
2016	—	`conf`	An FPGA-accelerated partial image matching engine for massive media data searching systems. VLSI Circuits Takashi Shimizu, Yasumoto Tomita, Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, David Thach, Takashi Miyoshi, Takayuki Baba, Yasuhiro Watanabe, Atsushi Ike
2016	—	`conf`	Memory reduction method for deep neural network training. MLSP Koichi Shirahata, Yasumoto Tomita, Atsushi Ike
2014	—	`conf`	A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura
2014	—	`conf`	What is a good way to expand a silicon value to a solution value? A-SSCC Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara
2010	J	`jnl`	A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2010	—	`conf`	A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
2010	J	`jnl`	A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2010	—	`conf`	A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. CICC Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune
2010	—	`conf`	A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
2010	J	`jnl`	Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2009	—	`conf`	Split capacitor DAC mismatch calibration in successive approximation ADC. CICC Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2008	—	`conf`	A dynamic offset control technique for comparator design in scaled CMOS technology. CICC Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2007	J	`jnl`	A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. IEEE J. Solid State Circuits Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2006	—	`conf`	A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. ISSCC Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2005	J	`jnl`	A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. IEEE J. Solid State Circuits Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda