Yasumitsu Orii

13 papers A* 1Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2023 — conf
Semiconductor Packaging Revolution in the Era of Chiplets : Keynote 1.
ITC-Asia
Yasumitsu Orii
2023 — conf
Semiconductor Packaging Revolution in the Era of Chiplets.
ICICDT
Yasumitsu Orii
2020 A* conf
Molecular Inverse-Design Platform for Material Industries.
KDD
Seiji Takeda, Toshiyuki Hama, Hsiang-Han Hsu, Victoria A. Piunova, Dmitry Zubarev, Daniel P. Sanders, Jed W. Pitera, Makoto Kogoh, Takumi Hongo, Yenwei Cheng, Wolf Bocanett, Hideaki Nakashika, Akihiro Fujita, Yuta Tsuchiya, Katsuhiko Hino, Kentaro Yano, Shuichi Hirose, Hiroki Toda, Yasumitsu Orii, Daiju Nakano
2020 J jnl
Molecular Inverse-Design Platform for Material Industries.
CoRR
Seiji Takeda, Toshiyuki Hama, Hsiang-Han Hsu, Victoria A. Piunova, Dmitry Zubarev, Daniel P. Sanders, Jed W. Pitera, Makoto Kogoh, Takumi Hongo, Yenwei Cheng, Wolf Bocanett, Hideaki Nakashika, Akihiro Fujita, Yuta Tsuchiya, Katsuhiko Hino, Kentaro Yano, Shuichi Hirose, Hiroki Toda, Yasumitsu Orii, Daiju Nakano
2019 J jnl
An Information Extraction and Knowledge Graph Platform for Accelerating Biochemical Discoveries.
CoRR
Matteo Manica, Christoph Auer, Valéry Weber, Federico Zipoli, Michele Dolfi, Peter W. J. Staar, Teodoro Laino, Costas Bekas, Akihiro Fujita, Hiroki Toda, Shuichi Hirose, Yasumitsu Orii
2015 — conf
Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration.
3DIC
Kuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii
2014 — conf
Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack.
3DIC
Keiji Matsumoto, Hiroyuki Mori, Yasumitsu Orii
2013 — conf
Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack.
3DIC
Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma, Hidekazu Kikuchi, Hiroyuki Mori, Yasumitsu Orii, Fumiaki Yamada, Kohei Fujihara, Junichi Takamatsu, Koji Kondo
2013 — conf
Thermo-mechanical evaluation of 3D packages.
3DIC
Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Hiroyuki Mori, Yasumitsu Orii
2011 — conf
Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package.
3DIC
Toru Ikeda, Masatoshi Oka, Shinya Kawahara, Noriyuki Miyazaki, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada
2011 — conf
Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration.
3DIC
Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Yasumitsu Orii, Katsuyuki Sakuma, Takahiro Kinoshita, Takashi Kawakami
2010 — conf
High density 3D integration by pre-applied Inter Chip Fill.
3DIC
Akihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma, Sayuri Kohara, Keiji Matsumoto, Hidekazu Kikuchi, Yasumitsu Orii, Toshiro Mitsuhashi, Fumiaki Yamada
2004 J jnl
Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation.
Microelectron. Reliab.
Ikuo Shohji, Hideo Mori, Yasumitsu Orii