Yasumasa Tsukamoto

36 papers A 2Journal 12Unranked 22

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Leakage Current Fluctuation of On/Off-State Stress in 3 nm Process and its Guard-band Compensation. IRPS Mitsuhiko Igarashi, Yuuki Uchida, Keiichiro Iwamoto, Yoshio Takazawa, Yasumasa Tsukamoto
2021	J	`jnl`	An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani, Kazutoshi Kobayashi
2020	—	`conf`	A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. VLSI Circuits Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka
2019	—	`conf`	Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process. IRPS Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani
2018	J	`jnl`	A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. IEEE Trans. Very Large Scale Integr. Syst. Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Tanaka, Koji Nii
2018	—	`conf`	A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process. A-SSCC Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii
2018	—	`conf`	Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET. IRPS Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii
2017	—	`conf`	NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator. A-SSCC Mitsuhiko Igarashi, Yoshio Takazawa, Yasumasa Tsukamoto, Kan Takeuchi, Koji Shibutani
2016	—	`conf`	A 5.92-Mb/mm A-SSCC Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii
2015	—	`conf`	1.8 Mbit/mm VLSIC Yasumasa Tsukamoto, Masao Morimoto, Makoto Yabuuchi, Miki Tanaka, Koji Nii
2014	—	`conf`	13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. ISSCC Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii
2014	J	`jnl`	28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. IEEE Trans. Very Large Scale Integr. Syst. Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa
2014	—	`conf`	A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. VLSIC Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato
2013	J	`jnl`	A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. IEEE J. Solid State Circuits Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki
2013	—	`conf`	A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. CICC Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Miki Tanaka, Shinji Tanaka, Koji Nii
2013	—	`conf`	A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda
2012	—	`conf`	A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki
2012	—	`conf`	A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. Asian Test Symposium Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto
2012	—	`conf`	A stable chip-ID generating physical uncloneable function using random address errors in SRAM. SoCC Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii
2012	—	`conf`	Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis. ISQED Takeshi Kida, Yasumasa Tsukamoto, Yuji Kihara
2012	—	`conf`	Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. ISQED Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu
2011	J	`jnl`	A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. IEEE J. Solid State Circuits Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, Kazumasa Yanagisawa
2011	A	`conf`	A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. ISLPED Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii
2011	—	`conf`	Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. CICC Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara
2010	—	`conf`	A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. ISSCC Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara
2009	J	`jnl`	Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. IEEE J. Solid State Circuits Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara
2008	J	`jnl`	A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
2008	J	`jnl`	A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE J. Solid State Circuits Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2008	J	`jnl`	A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. ISSCC Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2007	J	`jnl`	A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2005	—	`conf`	A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
2005	A	`conf`	Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2004	J	`jnl`	A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade
1995	J	`jnl`	3-D numerical modeling of thermal flow for insulating thin film using surface diffusion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Masato Fujinaga, I. Tottori, Tatsuya Kunikiyo, Tetsuya Uchida, Norihiko Kotani, Yasumasa Tsukamoto