Yasuhiro Takashima

39 papers B 1C 2Journal 12Unranked 24
YearRankTypeTitle / Venue / Authors
2026 J jnl
Complexity and Exact Solution of Set-Pair Routing Problem.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuhiro Takashima
2021 — conf
Theoretical and Experimental Analysis of Traveling Salesman Walk Problem.
APCCAS
Yasuhiro Takashima, Yuichi Nakamura
2018 — conf
Fast Approximate Algorithm for the Single Source Shortest Path with Lazy Update.
NGCAS
Tomohiro Takahashi, Yasuhiro Takashima
2018 — conf
Task Allocation and Scheduling Optimization in the Heterogeneous Core System.
NGCAS
Ryota Tsuchihashi, Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura
2016 — conf
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.
ISSCC
Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo
2016 J jnl
A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tieyuan Pan, Lian Zeng, Yasuhiro Takashima, Takahiro Watanabe
2016 — conf
A multi-functional memory unit with PLA-based reconfigurable decoder.
ReConFig
Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen
2016 J jnl
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, Yasuhiro Takashima
2016 — conf
PEVaS: Power and execution-time variation-aware scheduling for MPSoC.
NEWCAS
Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura
2015 — conf
Analytical placement for rectilinear blocks.
ASP-DAC
Yasuhiro Takashima
2015 J jnl
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi
2014 — conf
A randomized algorithm for the fixed-length routing problem.
APCCAS
Tieyuan Pan, Ran Zhang, Yasuhiro Takashima, Takahiro Watanabe
2014 — conf
Delay estimation method for correlated net delay variations.
APCCAS
Masatsugu Hosoki, Seiya Nagatsuka, Yasuhiro Takashima
2013 J jnl
An Effective Overlap Removable Objective for Analytical Placement.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima
2013 — conf
An acceleration method by GPGPU for analytical placement using quasi-Newton method.
ASICON
Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima
2012 — conf
Sub-path delay estimation for reconvergent path.
APCCAS
Seiya Nagatsuka, Yasuhiro Takashima
2010 C conf
Delay analysis of sub-path on fabricated chips by several path-delay tests.
ISCAS
Takanobu Shiki, Yasuhiro Takashima, Yuichi Nakamura
2010 J jnl
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.
Inf. Media Technol.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2010 J jnl
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.
IPSJ Trans. Syst. LSI Des. Methodol.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2009 — conf
A 172mm
ISSCC
Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama
2009 B conf
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.
FPL
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2008 — conf
Fast wire length estimation in obstructive block placement.
ICECS
Shuting Li, Tan Yan, Yasuhiro Takashima, Hiroshi Murata
2008 C conf
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.
ISCAS
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2008 J jnl
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2008 J jnl
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuko Hashizume, Yasuhiro Takashima, Yuichi Nakamura
2007 J jnl
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2007 J jnl
A Relocation Method for Circuit Modifications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura
2007 — conf
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks.
ASP-DAC
Tan Yan, Shuting Li, Yasuhiro Takashima, Hiroshi Murata
2006 — conf
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.
FPT
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2006 — conf
How does partitioning matter for 3D floorplanning?
ACM Great Lakes Symposium on VLSI
Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani
2006 J jnl
The Oct-Touched Tile: A New Architecture for Shape-Based Routing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2005 — conf
The oct-touched tile: a new architecture for shape-based routing.
ACM Great Lakes Symposium on VLSI
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2004 — conf
A device-level placement with multi-directional convex clustering.
ACM Great Lakes Symposium on VLSI
Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
2004 — conf
A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects.
ISCAS (4)
Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake
2004 — conf
Abstraction and optimization of consistent floorplanning with pillar block constraints.
ASP-DAC
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2004 — conf
Multi-level placement with circuit schema based clustering in analog IC layouts.
ASP-DAC
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
2002 — conf
Two-dimensional placement method based on divide-and-replacement.
APCCAS (2)
Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko
2000 — conf
Self-reforming routing for stochastic search in VLSI interconnection layout.
ASP-DAC
Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
1996 — conf
Detailed-Routability of FPGAs with Extremal Switch-Block Structures.
ED&TC
Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani