Yasuhiro Takahashi

102 papers A 4B 3C 5Misc 2Journal 40Unranked 48

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Classical simulability of quantum circuits followed by sparse classical post-processing. CoRR Yasuhiro Takahashi, Masayuki Miyamoto, Noboru Kunihiro
2026	J	`jnl`	Design and evaluation of low-power 6T adiabatic PUF circuit. IEICE Electron. Express Jiaming Liu, Yasuhiro Takahashi
2024	J	`jnl`	A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Trans. Circuits Syst. II Express Briefs Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2024	—	`conf`	A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2024	—	`conf`	A Design of PUF Circuit Using Adiabatic Logic. APCCAS Shoya Nagata, Yasuhiro Takahashi
2024	—	`conf`	A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. SOCC Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2024	J	`jnl`	A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectron. J. Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2024	—	`conf`	Design of Low-Power 6T Adiabatic PUF Circuit. APCCAS Jiaming Liu, Yasuhiro Takahashi
2024	—	`conf`	Low-Power, 25-Gb/s Active Voltage Current Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC Koji Tominaga, Yasuhiro Takahashi
2024	—	`conf`	Low-power and Small-area Transimpedance Amplifier with Active Inductor in 65 nm CMOS. APCCAS Takato Masuda, Yasuhiro Takahashi
2024	—	`conf`	Power-efficiency estimation of exponential horn driver circuit for low-power optical link. ISOCC Daisuke Ito, Masataka Furuta, Yasuhiro Takahashi, Makoto Nakamura
2023	J	`jnl`	10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. IEICE Electron. Express Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2023	—	`conf`	4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. ISOCC Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2023	—	`conf`	A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. ICECS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	—	`conf`	High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. ASICON Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	J	`jnl`	Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. IEICE Electron. Express Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2022	—	`conf`	A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. MWSCAS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2022	—	`conf`	A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. ICECS 2022 Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2022	—	`conf`	A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. MWSCAS Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2022	—	`conf`	Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. ICEIC Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2022	J	`jnl`	Divide-and-conquer verification method for noisy intermediate-scale quantum computation. Quantum Yuki Takeuchi, Yasuhiro Takahashi, Tomoyuki Morimae, Seiichiro Tani
2021	—	`conf`	A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. ICECS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2021	J	`jnl`	Classically simulating quantum circuits with local depolarizing noise. Theor. Comput. Sci. Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
2021	J	`jnl`	Power of uninitialized qubits in shallow quantum circuits. Theor. Comput. Sci. Yasuhiro Takahashi, Seiichiro Tani
2021	J	`jnl`	Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices. Sensors Câncio Monteiro, Yasuhiro Takahashi
2020	B	`conf`	Classically Simulating Quantum Circuits with Local Depolarizing Noise. MFCS Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
2020	J	`jnl`	Classically Simulating Quantum Circuits with Local Depolarizing Noise. CoRR Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
2020	J	`jnl`	Efficiently generating ground states is hard for postselected quantum computation. CoRR Yuki Takeuchi, Yasuhiro Takahashi, Seiichiro Tani
2020	—	`conf`	Message from the Technical Program Chairs iSES 2020. iSES Yasuhiro Takahashi, Tosiron Adegbija, Linga Reddy Cenkeramaddi
2020	J	`jnl`	Performance and Security Evaluation of S-Box Using Current-Pass Optimized Symmetric Pass Gate Adiabatic Logic. SN Comput. Sci. Hiroki Koyasu, Yasuhiro Takahashi
2020	J	`jnl`	Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function. SN Comput. Sci. Yasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal
2020	C	`conf`	Special Session: An Adiabatic Logic Based Silicon Physical Unclonable Function. ICCD Kohei Ogura, Yasuhiro Takahashi
2019	J	`jnl`	Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. IPSJ Trans. Syst. LSI Des. Methodol. Hiroki Koyasu, Yasuhiro Takahashi
2019	—	`conf`	Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor. ISVLSI Xiangyu Chen, Yasuhiro Takahashi
2019	—	`conf`	Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic. ISVLSI Hiroki Koyasu, Yasuhiro Takahashi
2019	J	`jnl`	Non-floating and low-power adiabatic logic circuit. IEICE Electron. Express Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
2019	—	`conf`	Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. ISVLSI Yasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal
2018	—	`conf`	5.3 GHz, 69.6 dBΩ Transimpedance Amplifier with Negative Impedance Converter. ISPACS Ryo Tagawa, Yasuhiro Takahashi
2018	—	`conf`	5.6 GHz, 61.7 dBΩ Transimpedance Amplifier Using Active Inductor in Shunt and Series Peaking Techniques. ISPACS Takumi Fukuura, Yasuhiro Takahashi
2018	—	`conf`	A New Adiabatic Logic without Charge Sharing Gate for Cryptographic Devices. ISPACS Ryosuke Ohashi, Yasuhiro Takahashi
2018	—	`conf`	Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices. ISPACS Câncio Monteiro, Apolinario Maria, Yasuhiro Takahashi
2018	A	`conf`	Power of Uninitialized Qubits in Shallow Quantum Circuits. STACS Yasuhiro Takahashi, Seiichiro Tani
2017	—	`conf`	Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. ECCTD Yuya Kojima, Toshikazu Sekine, Yasuhiro Takahashi
2017	—	`conf`	Low power Adiabatic Logic based on 2PC2AL. ICICDT Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
2017	—	`conf`	Operational amplifier based LC resonant circuit for adiabatic logic. MIXDES Yasuhiro Takahashi, Toshikazu Sekine, Mei Han
2016	J	`jnl`	Ancilla-driven instantaneous quantum polynomial time circuit for quantum supremacy. CoRR Yuki Takeuchi, Yasuhiro Takahashi
2016	J	`jnl`	Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits. Comput. Complex. Yasuhiro Takahashi, Seiichiro Tani
2016	J	`jnl`	Commuting quantum circuits with few outputs are unlikely to be classically simulatable. Quantum Inf. Comput. Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka
2016	J	`jnl`	Shallow Quantum Circuits with Uninitialized Ancillary Qubits. CoRR Yasuhiro Takahashi, Seiichiro Tani
2015	—	`conf`	A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2015	—	`conf`	An improved estimation method of 4 port S-parameters with 2 port measurements. ECCTD Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
2015	Misc	`conf`	Commuting Quantum Circuits with Few Outputs are Unlikely to be Classically Simulatable. COCOON Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka
2015	J	`jnl`	Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. IET Circuits Devices Syst. Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2015	—	`conf`	Power saving analysis of step-down buck converter using adiabatic switching principle. ISPACS Rui Manuel de Oliveira Amaral Sarmento, Yasuhiro Takahashi
2015	J	`jnl`	SPICE model of memristive device using Tukey window function. IEICE Electron. Express Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
2015	J	`jnl`	Two phase clocked subthreshold adiabatic logic circuit. IEICE Electron. Express Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2014	C	`conf`	An LSI implementation of a bit-parallel cellular multiplier over GF(2 ISCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2014	J	`jnl`	Commuting Quantum Circuits with Few Outputs are Unlikely to be Classically Simulatable. CoRR Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka
2014	—	`conf`	Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. APCCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2014	J	`jnl`	Hardness of classically simulating quantum circuits with unbounded Toffoli and fan-out gates. Quantum Inf. Comput. Yasuhiro Takahashi, Takeshi Yamazaki, Kazuyuki Tanaka
2014	—	`conf`	Power dissipation analysis of memristor for low power integrated circuit applications. APCCAS Haruki Ogata, Yasuhiro Takahashi, Toshikazu Sekine
2014	—	`conf`	Process variation verification of low-power secure CSSAL AES S-box circuit. MWSCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2014	—	`conf`	Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. APCCAS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2014	C	`conf`	Two phase clocking subthreshold adiabatic logic. ISCAS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2013	—	`conf`	An estimation method for the 3 port S-parameters with 1 port measurements. ECCTD Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
2013	J	`jnl`	Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. Microelectron. J. Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2013	A	`conf`	Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits. CCC Yasuhiro Takahashi, Seiichiro Tani
2013	C	`conf`	DPA resistance of charge-sharing symmetric adiabatic logic. ISCAS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2013	J	`jnl`	Dissemination of UTC(NICT) by Means of QZSS. IEEE Trans. Instrum. Meas. Thomas Hobiger, Yasuhiro Takahashi, Maho Nakamura, Tadahiro Gotoh, Shinichi Hama, Takashi Maruyama, Tsutomu Nagatsuma, Hiroyuki Noda, Motohisa Kishimoto, Kaoru Nakayama, Yasuhiro Ohki
2013	B	`conf`	Hardness of Classically Simulating Quantum Circuits with Unbounded Toffoli and Fan-Out Gates. MFCS Yasuhiro Takahashi, Takeshi Yamazaki, Kazuyuki Tanaka
2013	—	`conf`	Low power secure CSSAL bit-parallel multiplier over GF(2 ECCTD Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2013	—	`conf`	Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. TSP Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2012	—	`conf`	2PCDAL: Two-phase clocking dual-rail adiabatic logic. APCCAS Yasuhiro Takahashi, Zhongyu Luo, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
2012	—	`conf`	A low-power sense amplifier for adiabatic memory using memristor. APCCAS Yuki Urata, Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan
2012	J	`jnl`	LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine
2012	—	`conf`	Power-saving analysis of adiabatic logic in subthreshold region. ISPACS Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
2011	A	`conf`	Actual implementation of multi domain test: Further reduction of cost of test. ITC Yasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura
2011	J	`jnl`	Constant-Depth Exact Quantum Circuits for the OR and Threshold Functions CoRR Yasuhiro Takahashi, Seiichiro Tani
2011	—	`conf`	Low-power adiabatic SRAM. ISPACS Hides Jamima, Yasuhiro Takahashi, Toshikazu Sekine
2011	Misc	`conf`	Multi Domain Test: Novel test strategy to reduce the Cost of Test. VTS Yasuhiro Takahashi, Akinori Maeda
2011	—	`conf`	Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. ISPACS Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
2010	C	`conf`	4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2010	J	`jnl`	Quantum addition circuits and unbounded fan-out. Quantum Inf. Comput. Yasuhiro Takahashi, Seiichiro Tani, Noboru Kunihiro
2010	—	`conf`	Simple Sets of Measurements for Universal Quantum Computation and Graph State Preparation. TQC Yasuhiro Takahashi
2009	—	`conf`	4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. ECCTD Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2009	—	`conf`	A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. ICECS Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
2009	—	`conf`	Fundamental logics based on two phase clocked adiabatic static CMOS logic. ICECS Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2009	J	`jnl`	Quantum Arithmetic Circuits: A Survey. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Takahashi
2009	—	`conf`	Two phase clocked adiabatic static CMOS logic. SoC Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
2008	J	`jnl`	A fast quantum circuit for addition with few qubits. Quantum Inf. Comput. Yasuhiro Takahashi, Noboru Kunihiro
2007	J	`jnl`	A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
2007	J	`jnl`	The quantum fourier transform on a linear nearest neighbor architecture. Quantum Inf. Comput. Yasuhiro Takahashi, Noboru Kunihiro, Kazuo Ohta
2007	J	`jnl`	VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. IEICE Trans. Electron. Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
2006	—	`conf`	2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. APCCAS Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama
2006	J	`jnl`	A quantum circuit for shor's factoring algorithm using 2n + 2 qubits. Quantum Inf. Comput. Yasuhiro Takahashi, Noboru Kunihiro
2005	J	`jnl`	A linear-size quantum circuit for addition with no ancillary qubits. Quantum Inf. Comput. Yasuhiro Takahashi, Noboru Kunihiro
2005	—	`conf`	New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. ISCAS (2) Yasuhiro Takahashi, Michio Yokoyama
2003	J	`jnl`	Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Takahashi, Kei-ichi Konta, Kazukiyo Takahashi, Michio Yokoyama, Kazuhiro Shouno, Mitsuru Mizunuma
2003	B	`conf`	On the computational power of constant-depth quantum circuits with gates for addition. IEEE Congress on Evolutionary Computation Yasuhiro Takahashi, Yasuhito Kawano, Masahiro Kitagawa
2002	A	`conf`	An efficient dialogue control method using decision tree-based estimation of out-of-vocabulary word attributes. INTERSPEECH Yasuhiro Takahashi, Kohji Dohsaka, Kiyoaki Aikawa
1992	J	`jnl`	An integrated multimedia desktop communication and collaboration platform for broadband ISDN: the broadband ISDN group tele-working system. Comput. Commun. Rev. Tohru Hoshi, Yasuhiro Takahashi, Kenjiro Mori
1992	J	`jnl`	B-ISDN Multimedia Communication and Collaboration Platform Using Advanced Video Workstations to Support Cooperative Work. IEEE J. Sel. Areas Commun. Tohru Hoshi, Kenjiro Mori, Yasuhiro Takahashi, Yoshiyuki Nakayama, Takeshi Ishizaki