Yasuhiro Konishi

12 papers A 2Journal 10

Year	Rank	Type	Title / Venue / Authors
2005	J	`jnl`	Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. IEICE Trans. Electron. Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara
2004	J	`jnl`	A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. IEEE J. Solid State Circuits Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara
2000	J	`jnl`	A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE J. Solid State Circuits Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara
2000	J	`jnl`	A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. IEEE J. Solid State Circuits Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki
1998	J	`jnl`	400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
1994	A	`conf`	Testing 256k Word x 16 Bit Cache DRAM (CDRAM). ITC Yasuhiro Konishi, Toshiyuki Ogawa, Masaki Kumanoya
1993	J	`jnl`	Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
1992	J	`jnl`	A 100-MHz 4-Mb cache DRAM with fast copy-back scheme. IEEE J. Solid State Circuits Katsumi Dosaka, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara
1992	J	`jnl`	A 34-ns 16-Mb DRAM with controllable voltage down-converter. IEEE J. Solid State Circuits Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima
1992	A	`conf`	A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
1990	J	`jnl`	A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. IEEE J. Solid State Circuits Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara
1989	J	`jnl`	Analysis of coupling noise between adjacent bit lines in megabit DRAMs. IEEE J. Solid State Circuits Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara