Yasuhiko Taito

15 papers Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs.
ISSCC
Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono
2024 J jnl
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C.
IEEE J. Solid State Circuits
Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono
2022 — conf
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C.
VLSI Technology and Circuits
Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono
2022 J jnl
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm
IEEE J. Solid State Circuits
Masaya Nakano, Yoshinobu Kaneda, Satoru Nakanishi, Yasumitsu Murai, Yosuke Tashiro, Yasuhiko Taito, Tomoya Ogawa, Hidenori Mitani, Takashi Ito, Takashi Kono
2022 J jnl
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Amir Amirkhany, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito
2021 — conf
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier.
A-SSCC
Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono
2021 — conf
Session 30 Overview: Non-Volatile Memories Memory Subcommittee.
ISSCC
Yasuhiko Taito, Violante Moschiano, Shinichiro Shiratake
2020 J jnl
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age.
IEICE Trans. Electron.
Takashi Kono, Yasuhiko Taito, Hideto Hidaka
2019 — conf
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive.
VLSI Circuits
Akihiko Kanda, Takashi Kurafuji, Koichi Takeda, Tomoya Ogawa, Yasuhiko Taito, Kazuo Yoshihara, Masaya Nakano, Takashi Ito, Hiroyuki Kondo, Takashi Kono
2018 — ch.
SONOS Split-Gate eFlash Memory.
Embedded Flash Memory for Embedded Systems
Takashi Ito, Yasuhiko Taito
2016 — conf
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C.
ISSCC
Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2016 J jnl
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.
IEEE J. Solid State Circuits
Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2015 — conf
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C.
ISSCC
Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2003 J jnl
A Low Power Embedded DRAM Macro for Battery-Operated LSIs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki
2003 J jnl
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write.
IEEE J. Solid State Circuits
Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto