Yasuhiko Nakashima

206 papers A* 1A 1C 8Misc 6Journal 76Unranked 114

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Protocol-Aware P4 Pipeline for MQTT Security and Anomaly Mitigation in Edge IoT Systems. CoRR Bui Ngoc Thanh Binh, Pham Hoai Luan, Vu Trung Duong Le, Vu Tuan Hai, Yasuhiko Nakashima
2026	J	`jnl`	An FPGA Accelerator for Vision Transformer with Quantization and LUT-Based Operations. IEICE Trans. Inf. Syst. Cheng Xu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2026	J	`jnl`	Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security. CoRR Anh Kiet Pham, Van Truong Vo, Vu Trung Duong Le, Tuan Hai Vu, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima
2026	J	`jnl`	DystoHD: an area-efficient hyperdimensional computing system with dynamic hypervector generation for memory-constrained devices. J. Supercomput. Haoyu Tang, Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima
2026	J	`jnl`	Efficient Hardware Implementation of Robust Binary Neural Networks Using End-to-End Unipolar Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Babak Golbabaei, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2026	—	`conf`	Integrated Memory Grouping and Power-Aware MBIST Scheduling for MPSoCs. NG-RES@HiPEAC Koki Asahina, Yasuhiko Nakashima
2025	—	`conf`	A DNN-Oriented Rapid Simulation Framework for Digital Processing-In-Memory Architectures. SOCC Yirong Kan, Guangxian Zhu, Renyuan Zhang, Yasuhiko Nakashima
2025	—	`conf`	A Lightweight Transformer Model with Dynamic Sparse Mask for Neural Machine Translation. COOL CHIPS Nastaran Asadi, Babak Golbabaei, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2025	J	`jnl`	Benchmarking Variants of the Adam Optimizer for Quantum Machine Learning Applications. IEEE Open J. Comput. Soc. Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima
2025	J	`jnl`	CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima
2025	J	`jnl`	Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA. IEEE Access Takuto Ando, Yu Eto, Ayumu Takeuchi, Yasuhiko Nakashima
2025	J	`jnl`	Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA. CoRR Takuto Ando, Yu Eto, Ayumu Takeuchi, Yasuhiko Nakashima
2025	J	`jnl`	Energy Consumption Optimization of Multi-Dimensional U-Nets on CGLA. IEEE Access Thi Sang Duong, Ren Imamura, Tomoya Akabe, Yasuhiko Nakashima
2025	—	`conf`	Energy-Efficient FlashAttention Acceleration on CGLA. SOCC Ayumu Takeuchi, Yu Eto, Takuto Ando, Yasuhiko Nakashima
2025	—	`conf`	Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA. CANDAR Takuto Ando, Yu Eto, Ayumu Takeuchi, Yasuhiko Nakashima
2025	J	`jnl`	Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA. CoRR Takuto Ando, Yu Eto, Ayumu Takeuchi, Yasuhiko Nakashima
2025	—	`conf`	Energy-Efficient Llama3 Acceleration on a CGLA by Offloading Computational Kernels. SOCC Takuto Ando, Yu Eto, Ayumu Takeuchi, Yasuhiko Nakashima
2025	J	`jnl`	FQsun: A Configurable Wave Function-Based Quantum Emulator for Power-Efficient Quantum Simulations. IEEE Access Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Quoc Chuong Nguyen, Yasuhiko Nakashima
2025	—	`conf`	HPQEA: A Scalable and High-Performance Quantum Emulator with High-Bandwidth Memory for Diverse Algorithms Support. CANDAR Van Duy Tran, Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima
2025	J	`jnl`	IMAX: A Power-Efficient Multilevel Pipelined CGLA and Applications. IEEE Access Tomoya Akabe, Vu Trung Duong Le, Yasuhiko Nakashima
2025	—	`conf`	Implementation and Evaluation of Stable Diffusion on a General-Purpose CGLA Accelerator. MCSoC Takuto Ando, Yu Eto, Yasuhiko Nakashima
2025	J	`jnl`	Implementation and Evaluation of Stable Diffusion on a General-Purpose CGLA Accelerator. CoRR Takuto Ando, Yu Eto, Yasuhiko Nakashima
2025	—	`conf`	LLM Performance Bottlenecks on CGLA. SOCC Yu Eto, Takuto Ando, Ayumu Takeuchi, Yasuhiko Nakashima
2025	J	`jnl`	Lifelong Whole Slide Image Analysis: Online Vision-Language Adaptation and Past-to-Present Gradient Distillation. IEEE Access Doanh C. Bui, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Khang Nguyen, Yasuhiko Nakashima
2025	J	`jnl`	Lifelong Whole Slide Image Analysis: Online Vision-Language Adaptation and Past-to-Present Gradient Distillation. CoRR Doanh C. Bui, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Khang Nguyen, Yasuhiko Nakashima
2025	J	`jnl`	MINA: A Hardware-Efficient and Flexible Mini-InceptionNet Accelerator for ECG Classification in Wearable Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Hoai Luan Pham, Thi Diem Tran, Vu Trung Duong Le, Yasuhiko Nakashima
2025	—	`conf`	MMzk: 384-bit Low-Resource Montgomery Multiplier on FPGA for zk-SNARK. CANDAR Hikaru Okamoto, Vu Trung Duong Le, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima
2025	J	`jnl`	MRCA 2.0: An Area-Optimized Multigrained Reconfigurable Cryptographic Accelerator for Securing Blockchain-Based Internet of Things Systems. IEEE Micro Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Van Tinh Nguyen, Thi Diem Tran, Yasuhiko Nakashima
2025	J	`jnl`	MergeSlide: Continual Model Merging and Task-to-Class Prompt-Aligned Inference for Lifelong Learning on Whole Slide Images. CoRR Doanh C. Bui, Ba Hung Ngo, Hoai Luan Pham, Khang Nguyen, Maï K. Nguyen, Yasuhiko Nakashima
2025	J	`jnl`	Optimizing Matrix-Vector Operations With CGLA for High-Performance Approximate k-NN Search. IEEE Access Dohyun Kim, Yasuhiko Nakashima
2025	—	`conf`	Performance Evaluation of Flan-T5 in CGLA based Accelerators. SOCC Yu Eto, Takuto Ando, Yasuhiko Nakashima
2025	—	`conf`	Power Efficient Attention Acceleration on CGLA. SOCC Ayumu Takeuchi, Yasuhiko Nakashima
2025	J	`jnl`	Qimax: Efficient quantum simulation via GPU-accelerated extended stabilizer formalism. CoRR Vu Tuan Hai, Doanh C. Bui, Vu Trung Duong Le, Pham Hoai Luan, Yasuhiko Nakashima
2025	—	`conf`	Transfer-Based Strategies for Multi-Target Quantum Optimization. CANDARW Tuan Hai Vu, Doanh C. Bui, Vu Trung Duong Le, Pham Hoai Luan, Yasuhiko Nakashima
2025	—	`conf`	Ultra Low Latency Spiking Locally Competitive Algorithm for Spatio-temporal Data and Hierarchical Networks. CANDAR Takumi Kuwahara, Reon Oshio, Taiga Hirano, Mutsumi Kimura, Yasuhiko Nakashima
2025	—	`conf`	UniCrypt: Universal Crypto Engine with Optimized Resource Sharing for Security Applications. COOL CHIPS Vu Trung Duong Le, Hoai Luan Pham, Tuan Hai Vu, Van Duy Tran, Yasuhiko Nakashima
2025	J	`jnl`	ZeroSlide: Is Zero-Shot Classification Adequate for Lifelong Learning in Whole-Slide Image Analysis in the Era of Pathology Vision-Language Foundation Models? CoRR Doanh C. Bui, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Yasuhiko Nakashima
2025	—	`conf`	zk-STARKs in Action: Real-Time and Post-Quantum Verification for Banking Transactions. CANDARW Thanh Hai To, Vu-Trung Duong Le, Van Tinh Nguyen, Van-Tuan Luu, Hoai Luan Pham, Yasuhiko Nakashima
2024	J	`jnl`	A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array. IEEE Micro Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
2024	C	`conf`	A Fully-Parallel Reconfigurable Spiking Neural Network Accelerator with Structured Sparse Connections. ISCAS Mingyang Li, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2024	—	`conf`	An FPGA-Oriented Quantization Approach for Vision Transformer with LUT-Friendly Operations. CANDAR Cheng Xu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2024	—	`conf`	Benchmarking Classical and Quantum Optimizers for Quantum Simulator. CANDAR Vu Tuan Hai, Vu Trung Duong Le, Pham Hoai Luan, Yasuhiko Nakashima
2024	J	`jnl`	Bisection Neural Network Toward Reconfigurable Hardware Implementation. IEEE Trans. Neural Networks Learn. Syst. Yan Chen, Renyuan Zhang, Yirong Kan, Sa Yang, Yasuhiko Nakashima
2024	—	`conf`	CGLA: Coarse-Grained Linear Array for Multi-Hash Acceleration in Blockchain Mining. ISOCC Pham Hoai Luan, Vu Trung Duong Le, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima
2024	—	`conf`	Efficient Random Quantum Circuit Generator: A Benchmarking Approach for Quantum Simulators. RIVF Vu Tuan Hai, Vu Trung Duong Le, Pham Hoai Luan, Yasuhiko Nakashima
2024	—	`conf`	Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation. CANDARW Van Duy Tran, Tran Xuan Hieu Le, Thi Diem Tran, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Tinh Nguyen, Yasuhiko Nakashima
2024	J	`jnl`	Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation. CoRR Van Duy Tran, Tran Xuan Hieu Le, Thi Diem Tran, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Tinh Nguyen, Yasuhiko Nakashima
2024	J	`jnl`	FQsun: A Configurable Wave Function-Based Quantum Emulator for Power-Efficient Quantum Simulations. CoRR Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Quoc Chuong Nguyen, Yasuhiko Nakashima
2024	J	`jnl`	Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Vu Trung Duong Le, Hoai-Luan Pham, Thi Hong Tran, Yasuhiko Nakashima
2024	J	`jnl`	Fusion synapse by memristor and capacitor for spiking neuromorphic systems. Neurocomputing Takumi Kuwahara, Reon Oshio, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
2024	—	`conf`	Hator: A High-Efficiency CGRA-Based 32/64-Bit Hashing Accelerator with Real-Time Performance Analysis. MCSoC Hai Hau Nguyen, Pham Hoai Luan, Tuan Hai Vu, Van Duy Tran, Vu Trung Duong Le, Duc Khai Lam, Thi Diem Tran, Yasuhiko Nakashima
2024	—	`conf`	High-Efficiency RISC-V-Based Cryptographic Coprocessor for Security Applications. ISOCC Duc Hong An Le, Vu Trung Duong Le, Viet Anh Ho, Van Tinh Nguyen, Hoai Luan Pham, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima
2024	—	`conf`	Implementation and Evaluation of LLM on a CGLA. CANDAR Hitoaki Uetani, Yasuhiko Nakashima
2024	—	`conf`	Kyberator: A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-Kyber Accelerator for Quantum-Resistant Security Applications. ISOCC Nhat Nguyen Dinh, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Yasuhiko Nakashima
2024	—	`conf`	LI-RV: A Fast and Efficient RISC-V based Coprocessor for Lightweight Cryptography. ISOCC Ngoc Hung Nguyen, Duc Hong An Le, Vu Trung Duong Le, Van Tinh Nguyen, Tuan Hai Vu, Hoai Luan Pham, Yasuhiko Nakashima
2024	J	`jnl`	LiCryptor: High-Speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. Hoai Luan Pham, Vu Trung Duong Le, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima
2024	—	`conf`	MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements. COOL CHIPS Pham Hoai Luan, Hai Hau Nguyen, Vu Trung Duong Le, Thi Diem Tran, Tuan Hai Vu, Thi Hong Tran, Yasuhiko Nakashima
2024	—	`conf`	PESA: Power-Efficient SPHINCS+ Accelerator for Multi-Domain Security Applications on FPGA SoC. CANDAR Vu Trung Duong Le, Anh Kiet Pham, Hoai Luan Pham, Tuan Hai Vu, Yasuhiko Nakashima
2024	—	`conf`	Power-Efficient Acceleration of GCNs on Coarse-Grained Linear Arrays. COOL CHIPS Dohyun Kim, Koki Asahina, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2024	—	`conf`	Quantum Battery Optimization through Quantum Machine Learning Techniques. ISOCC Vu Tuan Hai, Vo Minh Kiet, Vu Trung Duong Le, Pham Hoai Luan, Le Bin Ho, Yasuhiko Nakashima
2024	J	`jnl`	Theoretical Analysis of the Efficient-Memory Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs. CoRR Tran Xuan Hieu Le, Hoai Luan Pham, Tuan Hai Vu, Vu Trung Duong Le, Yasuhiko Nakashima
2024	—	`conf`	Theoretical Analysis of the Memory-Efficient Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs. MCSoC Tran Xuan Hieu Le, Pham Hoai Luan, Vu Tuan Hai, Vu Trung Duong Le, Yasuhiko Nakashima
2024	—	`conf`	UCP: A Unified Cryptographic Processor for High Performance and Low Power Security Applications. ISOCC Vu Trung Duong Le, Hoai Luan Pham, Tuan Hai Vu, Van Duy Tran, Thi Diem Tran, Yasuhiko Nakashima
2023	—	`conf`	A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural Networks. SOCC Babak Golbabaei, Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2023	—	`conf`	An Ultra-Compact Calculation Unit with Temporal-Spatial Re-configurability. NEWCAS Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2023	—	`conf`	Efficient and High-Speed CGRA Accelerator for Cryptographic Applications. candar Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima
2023	—	`conf`	Energy-Efficient 3D Convolution Using Interposed Memory Accelerator eXtension 2 for Medical Image Processing. MICAD Ren Imamura, Guangxian Zhu, Thi Sang Duong, Hoai Luan Pham, Renyuan Zhang, Yasuhiko Nakashima
2023	—	`conf`	Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain. MWSCAS Pham Hoai Luan, Thi Sang Duong, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima
2023	J	`jnl`	Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications. IEEE Des. Test Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
2023	—	`conf`	High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing. MCSoC Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima
2023	J	`jnl`	Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform. IEICE Trans. Inf. Syst. Van-Cam Nguyen, Yasuhiko Nakashima
2023	J	`jnl`	Neuromorphic System Using Memcapacitors and Autonomous Local Learning. IEEE Trans. Neural Networks Learn. Syst. Mutsumi Kimura, Yuma Ishisaki, Yuta Miyabe, Homare Yoshida, Isato Ogawa, Tomoharu Yokoyama, Ken-Ichi Haga, Eisuke Tokumitsu, Yasuhiko Nakashima
2023	C	`conf`	Phase-Change Memory using Cu2GeTe3 and Multiple Writing Technique for Neuromorphic Systems. ICCE Shihori Akane, Isao Horiuchi, Yasushi Hiroshima, Yasuhiko Nakashima, Mutsumi Kimura
2023	—	`conf`	Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing. SOCC Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima
2023	—	`conf`	RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms. KSE Vu Trung Duong Le, Hoai Luan Pham, Thi Sang Duong, Thi Hong Tran, Quoc Duy Nam Nguyen, Yasuhiko Nakashima
2023	—	`conf`	Sensitivity Analysis of Memory Bandwidth on Column-superposed Versatile Linear CGRA. NEWCAS Tomoya Akabe, Ryotaro Funai, Yasuhiko Nakashima
2023	—	`conf`	Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing. RIVF Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Ren Imamura, Thi Hong Tran, Yasuhiko Nakashima
2023	—	`conf`	Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing. SOCC Reon Oshio, Takumi Kuwahara, Mutsumi Kimura, Yasuhiko Nakashima
2023	—	`conf`	Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission. MCSoC Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima
2023	—	`conf`	Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications. ICICDT Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Quoc Duy Nam Nguyen, Thi Sang Duong, Yasuhiko Nakashima
2022	—	`conf`	A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration. IPDPS Workshops Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
2022	—	`conf`	A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications. SBCCI Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
2022	J	`jnl`	A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator. IEEE Access Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
2022	—	`conf`	A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks. MWSCAS Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
2022	J	`jnl`	A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness. IEICE Trans. Inf. Syst. Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
2022	—	`conf`	A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training. COOL CHIPS Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
2022	—	`conf`	A Stochastic Coding Method of EEG Signals for Sleep Stage Classification. SOCC Guangxian Zhu, Huijia Wang, Yirong Kan, Zheng Chen, Ming Huang, Md. Altaf-Ul-Amin, Naoaki Ono, Shigehiko Kanaya, Renyuan Zhang, Yasuhiko Nakashima
2022	—	`conf`	Application and Evaluation of Quantization for Narrow Bit-width Resampling of Sequential Monte Carlo. SOCC Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima
2022	J	`jnl`	Application of Machine Learning to Environmental DNA Metabarcoding. IEEE Access Mutsumi Kimura, Hiroki Yamanaka, Yasuhiko Nakashima
2022	—	`conf`	CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining. SBCCI Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima
2022	J	`jnl`	Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator. IEEE Access Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
2022	—	`conf`	GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights. SOCC Man Wu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
2022	J	`jnl`	GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. IEICE Trans. Inf. Syst. Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima
2022	J	`jnl`	MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima
2021	J	`jnl`	A Feasibility Study of Multi-Domain Stochastic Computing Circuit. IEICE Trans. Electron. Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima
2021	J	`jnl`	A High-Performance Multimem SHA-256 Accelerator for Society 5.0. IEEE Access Thi Hong Tran, Hoai Luan Pham, Yasuhiko Nakashima
2021	—	`conf`	An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic. MWSCAS Van-Tinh Nguyen, Tieu-Khanh Luong, Emanuel M. Popovici, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima
2021	—	`conf`	Analysis of Fully-Pipelined CNN Implementation on FPGA and HBM2. CANDAR (Workshops) Van-Cam Nguyen, Yasuhiko Nakashima
2021	J	`jnl`	BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Thi Hong Tran, Hoai Luan Pham, Tri Dung Phan, Yasuhiko Nakashima
2021	J	`jnl`	DiaNet: An elastic neural network for effectively re-configurable implementation. Neurocomputing Man Wu, Yirong Kan, Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima
2021	J	`jnl`	Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. Integr. Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima
2021	J	`jnl`	Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks. IEICE Trans. Inf. Syst. Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
2021	—	`conf`	High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory. COOL CHIPS Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima
2021	J	`jnl`	MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security. IEEE Access Vu Trung Duong Le, Thi Hong Tran, Hoai Luan Pham, Duc Khai Lam, Yasuhiko Nakashima
2021	—	`conf`	Preliminary Evaluation for Multi-domain Spike Coding on Memcapacitive Neuromorphic Circuit. CANDAR (Workshops) Reon Oshio, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
2021	J	`jnl`	STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM. IEEE Access Van-Tinh Nguyen, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima
2021	—	`conf`	Speeding Up of CGRAs by Reshaping and Stochastic FMA. CANDAR (Workshops) Tomoya Akabe, Renyuan Zhang, Yasuhiko Nakashima
2021	—	`conf`	Training Low-Latency Spiking Neural Network through Knowledge Distillation. COOL CHIPS Sugahara Takuya, Renyuan Zhang, Yasuhiko Nakashima
2020	C	`conf`	A Compact and Accuracy-Reconfigurable Univariate RBF Kernel Based on Stochastic Logic. ISCAS Van-Tinh Nguyen, Tieu-Khanh Luong, Renyuan Zhang, Yasuhiko Nakashima
2020	—	`conf`	A Multi-grained Reconfigurable Accelerator for Approximate Computing. ISVLSI Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima
2020	—	`conf`	An Elastic Neural Network Toward Multi-Grained Re-configurable Accelerator. NEWCAS Man Wu, Yan Chen, Yirong Kan, Takeshi Nomura, Renyuan Zhang, Yasuhiko Nakashima
2020	—	`conf`	Bayes without Bayesian Learning for Resisting Adversarial Attacks. CANDAR Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
2020	J	`jnl`	Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing. IEICE Trans. Inf. Syst. Ryuta Shingai, Yuria Hiraga, Hisakazu Fukuoka, Takamasa Mitani, Takashi Nakada, Yasuhiko Nakashima
2020	J	`jnl`	Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth. IEICE Trans. Inf. Syst. Jun Iwamoto, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima
2020	J	`jnl`	Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining. IEEE Access Hoai Luan Pham, Thi Hong Tran, Tri Dung Phan, Vu Trung Duong Le, Duc Khai Lam, Yasuhiko Nakashima
2020	—	`conf`	Hybrid Stochastic Computing Circuits in Continuous Statistics Domain. SoCC Renyuan Zhang, Tati Erlina, Tinh Van Nguyen, Yasuhiko Nakashima
2020	—	`conf`	Speeding Up VBGMM By Using Logsumexp With the Approximate Exp-function. CANDAR (Workshops) Taku Honda, Hiroki Nishimoto, Yasuhiko Nakashima
2019	—	`conf`	A Programmable Approximate Calculation Unit Employing Time-Encoded Stochastic Computing Elements. CANDAR Workshops Van Tinh Nguyen, Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima
2019	—	`conf`	A Programmable Calculation Unit Employing Memcapacitor-based Neuromorphic Circuit. NEWCAS Yan Chen, Jing Zhang, Yingjie Zhang, Renyuan Zhang, Mutsumi Kimura, Yasuhiko Nakashima
2019	J	`jnl`	A ReRAM-Based Row-Column-Oriented Memory Architecture for Convolutional Neural Networks. IEICE Trans. Electron. Yan Chen, Jing Zhang, Yuebing Xu, Yingjie Zhang, Renyuan Zhang, Yasuhiko Nakashima
2019	—	`conf`	An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS. ACM Great Lakes Symposium on VLSI Tati Erlina, Yan Chen, Renyuan Zhang, Yasuhiko Nakashima
2019	J	`jnl`	An efficient ReRAM-based inference accelerator for convolutional neural networks via activation reuse. IEICE Electron. Express Yan Chen, Jing Zhang, Yuebing Xu, Yingjie Zhang, Renyuan Zhang, Yasuhiko Nakashima
2019	—	`conf`	DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon. SoCC Renyuan Zhang, Yan Chen, Takashi Nakada, Yasuhiko Nakashima
2019	—	`conf`	Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract. IEEE ICBC Van-Cam Nguyen, Hoai-Luan Pham, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima
2019	—	`conf`	Evaluation of Neuromorphic Hardware using Cellular Neural Networks and Oxide Semiconductors. IPDPS Workshops Hiroya Ikeda, Hiroki Yamane, Mutsumi Kimura, Yuki Shibayama, Yasuhiko Nakashima
2019	—	`conf`	Evaluation of a Chained Systolic Array with High-Speed Links. CANDAR Workshops Jun Iwamoto, Renyuan Zhang, Yasuhiko Nakashima
2019	—	`conf`	GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. CANDAR Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima
2019	—	`conf`	Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah. ICCBN Dai Long Hoang, Thi Hong Tran, Yasuhiko Nakashima
2019	—	`conf`	Neuro-inspired System with Crossbar Array of Amorphous Metal-Oxide-Semiconductor Thin-Film Devices as Self-plastic Synapse Units. ICONIP (2) Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
2019	J	`jnl`	Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems. CoRR Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Yasuhiko Nakashima
2019	J	`jnl`	Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
2019	C	`conf`	Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach. APCC Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima
2018	—	`conf`	A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract. GLOBECOM Workshops Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima
2018	J	`jnl`	A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. IEICE Trans. Inf. Syst. Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
2018	—	`conf`	A programmable analog calculation unit for vector computations. COOL CHIPS Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
2018	J	`jnl`	Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing. IEEE Micro Renyuan Zhang, Noriyuki Uetake, Takashi Nakada, Yasuhiko Nakashima
2018	—	`conf`	EMAXVR: A programmable accelerator employing near ALU utilization to DSA. COOL CHIPS Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima
2018	—	`conf`	Efficient Multitasking on FPGA Using HDL-Based Checkpointing. ARC Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima
2018	—	`conf`	Evaluation of Letter Reproduction System Using Cellular Neural Network and Oxide Semiconductor Synapses by Logic Simulation. CANDAR Workshops Hiroya Ikeda, Hiroki Yamane, Yuki Shibayama, Mutsumi Kimura, Yasuhiko Nakashima
2018	J	`jnl`	Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver. CoRR Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima
2018	—	`conf`	Hopfield Neural Network with Double-Layer Amorphous Metal-Oxide Semiconductor Thin-Film Devices as Crosspoint-Type Synapse Elements and Working Confirmation of Letter Recognition. ICONIP (7) Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
2018	J	`jnl`	Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima
2017	—	`conf`	A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing. CANDAR Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
2017	J	`jnl`	A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes. J. Commun. Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima
2017	Misc	`conf`	CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. FCCM Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
2017	J	`jnl`	Cellular neural network formed by simplified processing elements composed of thin-film transistors. Neurocomputing Mutsumi Kimura, Ryohei Morita, Sumio Sugisaki, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
2017	—	`conf`	Compression and Aggregation for Optimizing Information Transmission in Distributed CNN. CANDAR Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada, Yasuhiko Nakashima
2017	—	`conf`	Neuromorphic Hardware Using Simplified Elements and Thin-Film Semiconductor Devices as Synapse Elements - Simulation of Hopfield and Cellular Neural Network -. ICONIP (6) Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima
2016	—	`conf`	ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system. COOL Chips Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima
2016	—	`conf`	ASIC design of a low-complexity K-best Viterbi decoder for IoT applications. APCCAS Hiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima
2016	—	`conf`	CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing. CANDAR Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2016	—	`conf`	CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. CANDAR Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2016	—	`conf`	Exploiting Bloom Filters for Saving Power Consumption of Auto-Memoization Processor. CANDAR Masayoshi Fujii, Yuuki Sato, Tomoaki Tsumura, Yasuhiko Nakashima
2016	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Yasuhiko Nakashima
2016	—	`conf`	Letter Reproduction Simulator for Hardware Design of Cellular Neural Network Using Thin-Film Synapses - Crosspoint-Type Synapses and Simulation Algorithm. ICONIP (2) Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima
2016	—	`conf`	Performance Comparison of CGRA and Mobile GPU for Light-Field Image Processing. CANDAR Yuttakon Yuttakonkit, Yasuhiko Nakashima
2016	J	`jnl`	Performance Optimization of Light-Field Applications on GPU. IEICE Trans. Inf. Syst. Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2016	—	`conf`	Simplification of Processing Elements in Cellular Neural Networks - Working Confirmation Using Circuit Simulation. ICONIP (2) Mutsumi Kimura, Nao Nakamura, Tomoharu Yokoyama, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
2016	—	`conf`	Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs. CANDAR Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2015	—	`conf`	A CGRA-Based Approach for Accelerating Convolutional Neural Networks. MCSoC Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
2015	—	`conf`	A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations. CANDAR Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2015	—	`conf`	An Approximate Computing Stack Based on Computation Reuse. CANDAR Yuuki Sato, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima
2015	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Yasuhiko Nakashima
2015	—	`conf`	Lowering the complexity of k-means clustering by BFS-dijkstra method for graph computing. COOL Chips Anna Zhang, Jun Yao, Yasuhiko Nakashima
2015	J	`jnl`	Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. IEICE Trans. Inf. Syst. Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
2014	J	`jnl`	A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor. IEEE Micro Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka
2014	J	`jnl`	A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction. IEICE Trans. Inf. Syst. Jun Yao, Yasuhiko Nakashima, Naveen Devisetti, Kazuhiro Yoshimura, Takashi Nakada
2014	—	`conf`	A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit. COOL Chips Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka
2014	—	`conf`	A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration. COOL Chips Yuttakon Yuttakonkit, Jun Yao, Yasuhiko Nakashima
2014	—	`conf`	An implementation of Auto-Memoization mechanism on ARM-based superscalar processor. ISSoC Yuuki Shibata, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima
2014	Misc	`conf`	Better-Than-DMR Techniques for Yield Improvement. FCCM Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima
2014	—	`conf`	Emulator-oriented tiny processors for unreliable post-silicon devices: A case study. ASP-DAC Yuko Hara-Azumi, Masaya Kunimoto, Yasuhiko Nakashima
2014	—	`conf`	Hinting for Auto-Memoization Processor Based on Static Binary Analysis. CANDAR Takanori Tsumura, Yuuki Shibata, Kazutaka Kamimura, Tomoaki Tsumura, Yasuhiko Nakashima
2014	—	`conf`	Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. CANDAR Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
2014	J	`jnl`	Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults. IEICE Trans. Inf. Syst. Yukihiro Sasagawa, Jun Yao, Yasuhiko Nakashima
2013	—	`conf`	CAM Size Reduction Method for Auto-memorization Processor by Considering Characteristics of Loops. CANDAR Yuuki Shibata, Kazutaka Kamimura, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima
2013	—	`conf`	HW/SW approaches to accelerate GRAPES in an FU array. COOL Chips Wei Wang, Jun Yao, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, Weimin Zheng
2013	J	`jnl`	Selective Check of Data-Path for Effective Fault Tolerance. IEICE Trans. Inf. Syst. Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima
2013	J	`jnl`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. IEICE Trans. Inf. Syst. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	Misc	`conf`	A Speed-up Technique for an Auto-Memoization Processor by Reusing Partial Results of Instruction Regions. ICNC Kazutaka Kamimura, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima
2012	—	`conf`	Introducing OVP awareness to achieve an efficient permanent defect locating. NANOARCH Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima
2012	J	`jnl`	Quantum Walks on the Line with Phase Parameters. IEICE Trans. Inf. Syst. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	J	`jnl`	RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima
2012	J	`jnl`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication CoRR Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	C	`conf`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. TAMC Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	J	`jnl`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. Electron. Colloquium Comput. Complex. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2011	—	`conf`	A hybrid model of speculative execution and scout threading for auto-memoization processor. SoC Tomoki Ikegaya, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima
2011	J	`jnl`	An Instruction Mapping Scheme for FU Array Accelerator. IEICE Trans. Inf. Syst. Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima
2011	—	`conf`	An efficient and reliable 1.5-way processor by fusion of space and time redundancies. DSN Workshops Jun Yao, Ryoji Watanabe, Kazuhiro Yoshimura, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima
2011	J	`jnl`	An efficient conversion of quantum circuits to a linear nearest neighbor architecture. Quantum Inf. Comput. Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2011	Misc	`conf`	Input Entry Integration for an Auto-Memoization Processor. ICNC Ryosuke Oda, Tatsuhiro Yamada, Tomoki Ikegaya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima
2011	—	`conf`	LAPP: A Low Power Array Accelerator with Binary Compatibility. IPDPS Workshops Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima
2010	C	`conf`	A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. PRDC Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi
2010	Misc	`conf`	A Speed-Up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations. ICNC Tomoki Ikegaya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima
2010	—	`conf`	An Instruction Decomposition Method for Reconfigurable Decoders. IWIA Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima
2009	C	`conf`	A Speculative Technique for Auto-Memoization Processor with Multithreading. PDCAT Yushi Kamiya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima
2009	J	`jnl`	Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition. Quantum Inf. Comput. Yumi Nakajima, Yasuhito Kawano, Hiroshi Sekigawa, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2008	C	`conf`	A Functional Unit with Small Variety of Highly Reliable Cells. PRDC Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2007	—	`conf`	A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. ARC Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2007	—	`conf`	Design and evaluation of an auto-memoization processor. Parallel and Distributed Computing and Networks Tomoaki Tsumura, Ikuma Suzuki, Yasuki Ikeuchi, Hiroshi Matsuo, Hiroshi Nakashima, Yasuhiko Nakashima
2005	—	`conf`	Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption. ISHPC Jun Yao, Hajime Shimada, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita
2004	—	`conf`	An Integrated System for Distributed Bioinformatics Environment on Grids. LSGRID Kenji Satou, Yasuhiko Nakashima, Shin'ichi Tsuji, Xavier Défago, Akihiko Konagaya
2004	Misc	`conf`	Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing. PDPTA Motohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita
2004	—	`conf`	Simulating realistic force and shape of virtual cloth with adaptive meshes and its parallel implementation in OpenMP. Parallel and Distributed Computing and Networks Alam Mujahid, Koh Kakusho, Michihiko Minoh, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita
2001	A*	`conf`	A high-speed dynamic instruction scheduling scheme for superscalar processors. MICRO Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori
1995	A	`conf`	Scalar Processor of the VPP500 Parallel Supercomputer. International Conference on Supercomputing Yasuhiko Nakashima, Toshiaki Kitamura, Hideo Tamura, Masaaki Takiuchi, Ken'ichi Miura