Yasuhiko Hagihara

14 papers Journal 9Unranked 5

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Fingertip-Size Optical Module, "Optical I/O Core", and Its Application in FPGA. IEICE Trans. Electron. Takahiro Nakamura, Kenichiro Yashiki, Kenji Mizutani, Takaaki Nedachi, Junichi Fujikata, Masatoshi Tokushima, Jun Ushida, Masataka Noguchi, Daisuke Okamoto, Yasuyuki Suzuki, Takanori Shimizu, Koichi Takemura, Akio Ukita, Yasuhiro Ibusuki, Mitsuru Kurihara, Keizo Kinoshita, Tsuyoshi Horikawa, Hiroshi Yamaguchi, Junichi Tsuchida, Yasuhiko Hagihara, Kazuhiko Kurata
2016	—	`conf`	25-Gbps error-free operation of chip-scale Si-photonics optical transmitter over 70°C with integrated quantum dot laser. OFC Kenichiro Yashiki, Kenji Mizutani, Jun Ushida, Yasuyuki Suzuki, Mitsuru Kurihara, Masatoshi Tokushima, Junichi Fujikata, Yasuhiko Hagihara, Kazuhiko Kurata
2016	J	`jnl`	25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores. IEICE Trans. Electron. Kenichiro Yashiki, Toshinori Uemura, Mitsuru Kurihara, Yasuyuki Suzuki, Masatoshi Tokushima, Yasuhiko Hagihara, Kazuhiko Kurata
2015	—	`conf`	5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF. OFC Kenichiro Yashiki, Yasuyuki Suzuki, Yasuhiko Hagihara, Mitsuru Kurihara, Masatoshi Tokushima, Junichi Fujikata, Akio Ukita, Koichi Takemura, Takanori Shimizu, Daisuke Okamoto, Jun Ushida, Shigeki Takahashi, Toshinori Uemura, Makoto Okano, Junichi Tsuchida, Takaaki Nedachi, Makoto Fushimi, Ichiro Ogura, Jun Inasaka, Kazuhiko Kurata
2015	—	`conf`	Optical I/O core transmitter with high tolerance to optical feedback using quantum dot laser. ECOC Kenji Mizutani, Kenichiro Yashiki, Mitsuru Kurihara, Yasuyuki Suzuki, Yasuhiko Hagihara, Nobuaki Hatori, Takanori Shimizu, Yutaka Urino, Takahiro Nakamura, Kazuhiko Kurata, Yasuhiko Arakawa
2008	J	`jnl`	A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. IEEE J. Solid State Circuits Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara
2006	J	`jnl`	A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE J. Solid State Circuits Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake
2006	J	`jnl`	An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques. IEICE Trans. Electron. Masahiro Nomura, Taku Ohsawa, Koichi Takeda, Yoetsu Nakazawa, Yoshinori Hirota, Yasuhiko Hagihara, Naoki Nishi
2006	J	`jnl`	Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. IEEE J. Solid State Circuits Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara
2006	J	`jnl`	Domino Logic Synthesis System and its Applications. J. Circuits Syst. Comput. Ko Yoshikawa, Shigeto Inui, Yasuhiko Hagihara, Yuichi Nakamura, Takeshi Yoshimura
2006	—	`conf`	Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. ISSCC Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake
2004	—	`conf`	Timing optimization by replacing flip-flops to latches. ASP-DAC Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura
1997	J	`jnl`	Floating-point datapaths with online built-in self speed test. IEEE J. Solid State Circuits Yasuhiko Hagihara, Shigeto Inui, Fuyuki Okamoto, Masato Nishida, Toshihiko Nakamura, Hachiro Yamada
1991	J	`jnl`	A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI. IEEE J. Solid State Circuits Fuyuki Okamoto, Yasuhiko Hagihara, Chie Ohkubo, Naoki Nishi, Hachiro Yamada, Tadayoshi Enomoto