Yasuaki Nishitani

21 papers B 1Journal 13Unranked 7
YearRankTypeTitle / Venue / Authors
2024 J jnl
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
IEICE Trans. Inf. Syst.
Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
2023 — conf
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
ISMVL
Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
2018 J jnl
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
2016 — conf
New Two-Qubit Gate Library with Entanglement.
ISMVL
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
2014 J jnl
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
IEICE Trans. Inf. Syst.
Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani
2014 J jnl
The firing squad synchronization problem with sub-generals.
Inf. Process. Lett.
Kazuya Yamashita, Yasuaki Nishitani, Sadaki Hirose, Satoshi Okawa, Nobuyasu Osato
2011 — conf
A Testable Realization for Decimal Multipliers.
ISMVL
Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura
2010 J jnl
The Firing Squad Synchronization Problems for Number Patterns on a Seven-Segment Display and Segment Arrays.
IEICE Trans. Inf. Syst.
Kazuya Yamashita, Mitsuru Sakai, Sadaki Hirose, Yasuaki Nishitani
2009 J jnl
Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions.
J. Circuits Syst. Comput.
Takashi Hirayama, Yasuaki Nishitani
2006 — conf
Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions.
DELTA
Takashi Hirayama, Yasuaki Nishitani
2006 — conf
Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation.
APCCAS
Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani
2002 J jnl
A Faster Algorithm of Minimizing AND-EXOR Expressions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
2002 — conf
A faster algorithm of minimizing AND-EXOR expressions.
APCCAS (2)
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
1999 — conf
Speedup of Lockout-Free Mutual Exclusion Algorithms.
ISPAN
Yoshihide Igarashi, Yasuaki Nishitani
1999 J jnl
Speedup of the n-Process Mutual Exclusion Algorithm.
Parallel Process. Lett.
Yoshihide Igarashi, Yasuaki Nishitani
1996 J jnl
A Probably Optimal Embedding of Hyper-Rings in Hypercubes.
Inf. Process. Lett.
Koji Obokata, Yasuaki Nishitani, Yoshihide Igarashi
1996 J jnl
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions.
Syst. Comput. Jpn.
Takashi Hirayama, Yasuaki Nishitani
1995 B conf
Embeddings of Hyper-Rings in Hypercubes.
ISAAC
Yukihiro Hamada, Aohan Mei, Yasuaki Nishitani, Yoshihide Igarashi
1992 J jnl
Graph representation of logic functions to design two-level MOS networks.
Syst. Comput. Jpn.
Yasuaki Nishitani, Kensuke Shimizu, Masahiko Nagumo
1982 J jnl
On Universality of Concurrent Expressions with Synchronization Primitives.
Theor. Comput. Sci.
T. Ito, Yasuaki Nishitani
1981 J jnl
The Firing Squad Synchronization Problem for Graphs.
Theor. Comput. Sci.
Yasuaki Nishitani, Namio Honda