Yaseer Arafat Durrani

16 papers C 1Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2021 J jnl
Efficient power macromodeling approach for an IP-based SoC system using discrete water cycle algorithm.
Turkish J. Electr. Eng. Comput. Sci.
Faisal Siddiq, Yaseer Arafat Durrani
2018 J jnl
Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs.
J. Circuits Syst. Comput.
Yaseer Arafat Durrani
2016 J jnl
Efficient power analysis approach and its application to system-on-chip design.
Microprocess. Microsystems
Yaseer Arafat Durrani, Teresa Riesgo
2014 J jnl
High-Level Power Analysis for Intellectual Property-Based Digital Systems.
Circuits Syst. Signal Process.
Yaseer Arafat Durrani, Teresa Riesgo
2014 J jnl
Power estimation for intellectual property-based digital systems at the architectural level.
J. King Saud Univ. Comput. Inf. Sci.
Yaseer Arafat Durrani, Teresa Riesgo
2013 J jnl
High-Level Power Analysis for Intellectual Property-Based Digital Systems.
J. Low Power Electron.
Yaseer Arafat Durrani, Teresa Riesgo
2011 — conf
Efficient power macromodeling technique for conventional MOS transistors.
ICEEI
Yaseer Arafat Durrani
2009 J jnl
Power estimation technique for DSP architectures.
Digit. Signal Process.
Yaseer Arafat Durrani, Teresa Riesgo
2008 — —
Power Macro-modelling for IP-based Digital Systems at Register Transfer Level: Macromodelado del consumo de sistemas digitales basados en IPs descritos a nivel de transferencia de registros.
Yaseer Arafat Durrani
2007 J jnl
Architectural Power Analysis for Intellectual Property-Based Digital System.
J. Low Power Electron.
Yaseer Arafat Durrani, Teresa Riesgo
2007 C conf
Efficient Power Macromodeling Technique for IP-Based Digital System.
ISCAS
Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo
2007 — conf
LUT-Based Power Macromodeling Technique for DSP Architectures.
ICECS
Yaseer Arafat Durrani, Teresa Riesgo
2006 — conf
Power Estimation for IP-Based Modules.
SoC
Yaseer Arafat Durrani, Teresa Riesgo
2006 — conf
Power Macromodeling for High Level Power Estimation.
ReCoSoC
Yaseer Arafat Durrani, Teresa Riesgo
2006 — conf
Power Macromodeling for IP Modules.
ICECS
Yaseer Arafat Durrani, Teresa Riesgo
2006 — conf
Power estimation for register transfer level by genetic algorithm.
ICINCO-RA
Yaseer Arafat Durrani, Teresa Riesgo, Felipe Machado