Yarui Peng

20 papers A* 4A 5Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System.
ACM Trans. Design Autom. Electr. Syst.
Zhen Zhuang, Weishiun Hung, M. D. Arafat Kabir, Yarui Peng, Tsung-Yi Ho
2022 J jnl
Design Challenges of Intrachiplet and Interchiplet Interconnection.
IEEE Des. Test
Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, Xiaohang Wang
2021 — conf
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design.
ACM Great Lakes Symposium on VLSI
M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
2021 A conf
Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation.
ICCAD
Imam Al Razi, Quang Le, H. Alan Mantooth, Yarui Peng
2021 — conf
Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization.
VLSI-DAT
M. D. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho, Yarui Peng
2020 — conf
Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools.
ASP-DAC
M. D. Arafat Kabir, Yarui Peng
2020 A conf
Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design.
ICCAD
M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
2020 — conf
Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study.
SoCC
M. D. Arafat Kabir, Yarui Peng
2017 J jnl
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning.
IEEE Trans. Very Large Scale Integr. Syst.
Moongon Jung, Taigon Song, Yarui Peng, Sung Kyu Lim
2016 J jnl
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim
2015 A* conf
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
DAC
Yarui Peng, Bon Woong Ku, Youn-Sik Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Sung Kyu Lim
2015 A conf
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs.
ICCAD
Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
2015 J jnl
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yarui Peng, Dusan Petranovic, Sung Kyu Lim
2014 A* conf
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling.
DAC
Yarui Peng, Dusan Petranovic, Sung Kyu Lim
2014 A* conf
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective.
DAC
Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, Sung Kyu Lim
2014 J jnl
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
2013 A conf
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs.
ISLPED
Sandeep Kumar Samal, Yarui Peng, Yang Zhang, Sung Kyu Lim
2013 A* conf
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs.
DAC
Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim
2013 A conf
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.
ICCAD
Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
2004 — conf
A Framework of Total Performance Improvement and Transaction Cost-driven Business Process Outsourcing Strategy.
PACIS
Yarui Peng, Wenhua Hou