Yaoyu Tao

30 papers A* 4A 1B 1C 6Journal 14Unranked 4
YearRankTypeTitle / Venue / Authors
2025 C conf
ASMA: An Anisotropy Scaling Memristor-Based Accelerator for LLM Inference.
ICCD
Zijian Xiong, Xiangrui Yang, Yuhang Zhang, Yue Zhou, Jianguo Yang, Yaoyu Tao, Xiangshui Miao, Yuhui He
2025 J jnl
Energy-Efficient Online Training with In Situ Parallel Computing on Electrochemical Memory Arrays.
Adv. Intell. Syst.
Yingming Lu, Zhen Yang, Yaoyu Tao, Lei Cai, Teng Zhang, Longhao Yan, Ru Huang, Yuchao Yang
2025 J jnl
Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory.
CoRR
Daijing Shi, Yihang Zhu, Anjunyi Fan, Yaoyu Tao, Yuchao Yang, Bonan Yan
2025 A* conf
PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference.
HPCA
Yihan Fu, Anjunyi Fan, Wenshuo Yue, Hongxiao Zhao, Daijing Shi, Qiuping Wu, Jiayi Li, Xiangyu Zhang, Yaoyu Tao, Yuchao Yang, Bonan Yan
2024 J jnl
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.
IEEE J. Solid State Circuits
Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang
2024 A* conf
MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads.
MICRO
Yihang Zhu, Lei Cai, Lianfeng Yu, Anjunyi Fan, Longhao Yan, Zhaokun Jing, Bonan Yan, Pek Jun Tiw, Yuqi Li, Yaoyu Tao, Yuchao Yang
2023 A conf
Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search.
FPGA
Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Yuchao Yang
2023 — conf
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm
VLSI Technology and Circuits
Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang
2023 J jnl
Fast and reconfigurable sort-in-memory system enabled by memristors.
CoRR
Lianfeng Yu, Yaoyu Tao, Teng Zhang, Zeyu Wang, Xile Wang, Zelun Pan, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Yihang Zhu, Bonan Yan, Yuchao Yang
2023 J jnl
Hadamard product-based in-memory computing design for floating point neural network training.
Neuromorph. Comput. Eng.
Anjunyi Fan, Yihan Fu, Yaoyu Tao, Zhonghua Jin, Haiyue Han, Huiyu Liu, Yaojun Zhang, Bonan Yan, Yuchao Yang, Ru Huang
2023 A* conf
eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs.
HPCA
Junkang Zhu, Yaoyu Tao, Zhengya Zhang
2022 J jnl
An Automated FPGA-based Framework for Rapid Prototyping of Nonbinary LDPC Codes.
CoRR
Yaoyu Tao, Qi Wu
2022 J jnl
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes.
CoRR
Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
2022 C conf
Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm.
ISCAS
Lianfeng Yu, Zhaokun Jing, Yuchao Yang, Yaoyu Tao
2022 J jnl
Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm.
CoRR
Lianfeng Yu, Zhaokun Jing, Yuchao Yang, Yaoyu Tao
2022 J jnl
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer.
CoRR
Yaoyu Tao, Zhengya Zhang
2022 C conf
High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder.
ISCAS
Yaoyu Tao, Cedric Choi
2022 J jnl
High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder.
CoRR
Yaoyu Tao, Cedric Choi
2021 J jnl
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture.
IEEE J. Solid State Circuits
Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
2021 B conf
DNC-Aided SCL-Flip Decoding of Polar Codes.
GLOBECOM
Yaoyu Tao, Zhengya Zhang
2021 J jnl
DNC-Aided SCL-Flip Decoding of Polar Codes.
CoRR
Yaoyu Tao, Zhengya Zhang
2021 A* conf
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer.
MICRO
Yaoyu Tao, Zhengya Zhang
2019 — conf
A 3.25Gb/s, 13.2pJ/b, 0.64mm
VLSI Circuits
Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
2019 C conf
An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes.
ISCAS
Yaoyu Tao, Qi Wu
2019 J jnl
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
2015 J jnl
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating.
IEEE J. Solid State Circuits
Youn Sung Park, Yaoyu Tao, Zhengya Zhang
2014 — conf
A 4.68Gb/s belief propagation polar decoder with bit-splitting register file.
VLSIC
Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
2013 — conf
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating.
ISSCC
Youn Sung Park, Yaoyu Tao, Zhengya Zhang
2013 C conf
Efficient in situ error detection enabling diverse path coverage.
ISCAS
Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang
2012 C conf
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders.
ISCAS
Yaoyu Tao, Youn Sung Park, Zhengya Zhang