Yao Lu

21 papers A* 4A 5B 1Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
A New Benchmark for the Appropriate Evaluation of RTL Code Optimization.
CoRR
Yao Lu, Shang Liu, Hangan Zhou, Wenji Fang, Qijun Zhang, Zhiyao Xie
2026 — conf
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework.
ASP-DAC
Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie
2025 A* conf
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis.
DAC
Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie
2025 J jnl
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis.
CoRR
Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie
2025 A* conf
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling.
DAC
Qijun Zhang, Yao Lu, Mengming Li, Zhiyao Xie
2025 — conf
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling.
ASP-DAC
Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie
2025 A conf
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment.
ICCAD
Wenji Fang, Wang Jing, Yao Lu, Shang Liu, Zhiyao Xie
2025 A conf
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions.
ICCAD
Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie
2025 A* conf
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph.
DAC
Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025 J jnl
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph.
CoRR
Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025 A* conf
Profile-Guided Temporal Prefetching.
ISCA
Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie
2025 J jnl
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2025 J jnl
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework.
CoRR
Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie
2025 — conf
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage.
ASP-DAC
Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie
2025 J jnl
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2024 A conf
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation.
ICCAD
Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie
2024 B conf
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model.
ASPDAC
Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie
2024 A conf
Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies.
ISLPED
Yao Lu, Qijun Zhang, Zhiyao Xie
2023 A conf
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.
ICCAD
Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023 J jnl
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.
CoRR
Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023 J jnl
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.
CoRR
Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie