Yao-Wen Chang - RankMe

408 papers A* 102A 92B 1C 13Journal 126Unranked 67

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Efficient High-Fidelity Warpage Modeling for Advanced Packaging Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yu Lo, MaoZe Liu, Yao-Wen Chang
2026	J	`jnl`	Modern Automatic PCB Placement With Complex Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chien-Hao Tsou, Sheng-Yah Lin, Wei-Chen Hung, Yao-Wen Chang
2026	J	`jnl`	Redistribution Layer Routing With Dynamic via Insertion Under Irregular via Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Je-Wei Chuang, Zong-Han Wu, Bo-Ying Huang, Yao-Wen Chang
2026	J	`jnl`	Simultaneous Power and Signal PCB Routing Considering Complex Clearance Constraints With Arbitrary Wire Widths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao-Yun Chang, Yao-Wen Chang
2026	—	`conf`	Subgraph-based Qubit Mapping for Noisy Intermediate-Scale Quantum Computing. ASP-DAC Junyi Gao, Wei-Hsiang Tseng, Yao-Wen Chang
2025	J	`jnl`	A Matching-Based Escape Routing Algorithm With Variable Design Rules and Multiple Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuandong Chen, Disi Lin, Qinghai Liu, Huan He, Zhifeng Lin, Genggeng Liu, Jianli Chen, Yao-Wen Chang
2025	A	`conf`	Advanced Packaging Warpage Modeling with DeepONet-Based Operator Learning. ICCAD Shao-Yu Lo, Che-Ming Chang, Yao-Wen Chang
2025	A*	`conf`	Clearance-Constrained PCB Global Placement with Heterogeneous Components. DAC Yan-Jen Chen, Wei-Kai Huang, Chung-Ting Tsai, Chiao-Yu Ou, Yao-Wen Chang
2025	A*	`conf`	Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-oriented Components. DAC Chiao-Yu Ou, Yan-Jen Chen, Yao-Wen Chang
2025	J	`jnl`	From Classical Algorithms to AI: Evolving Trends in VLSI Physical Design Automation. IEEE Des. Test David Z. Pan, Yao-Wen Chang, Chen-Hao Hsu, Yang Hsu
2025	A*	`conf`	Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization. DAC Chien-Hao Tsou, Zhu-Xun Lee, Yao-Wen Chang
2025	A*	`conf`	Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells. DAC Cheng-Yen Li, Chuan-Chi Su, Zheng-Wei Chen, Shao-Hsiang Chen, Yao-Wen Chang
2025	A*	`conf`	Late Breaking Results: Scalable GPU-Friendly Parallelization for Sweep-Based Maze Routing. DAC Cheng-Yu Chiang, Zong-Ying Cai, Chao-Chi Lan, Yan-Jen Chen, Yang Hsu, Yao-Wen Chang, Hung-Ming Chen
2025	A*	`conf`	Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging. DAC Min-Hung Chen, Cheng-Yen Li, Chuan-Chi Su, Yao-Wen Chang, Tung-Chieh Chen
2025	—	`conf`	Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization. ASP-DAC Cheng-Yu Chiang, Yi-Hsien Chiang, Chao-Chi Lan, Yang Hsu, Che-Ming Chang, Shao-Chi Huang, Sheng-Hua Wang, Yao-Wen Chang, Hung-Ming Chen
2025	A	`conf`	Parallel Non-Integer Multiple-Cell-Height Node Remapping. ICCAD Zong-Han Wu, Bo-Ying Huang, Yu-Chen Chen, Yao-Wen Chang
2025	A	`conf`	Performance-Driven Pre-Assignment Routing for High-Speed Package Designs. ICCAD Shao-Hsiang Chen, Zeng-Wei Chen, Po-Jen Lin, Hung-Jen Hsu, Hsin-Ying Lin, Yung-Hsiang Chuang, Huang-Yu Chen, Jim Chang, Yao-Wen Chang
2025	J	`jnl`	Physical Design for Heterogeneous Integration: Challenges and Opportunities. IEEE Des. Test Yao-Wen Chang, David Z. Pan
2025	—	`conf`	Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models. ASP-DAC Wei-Yao Kao, Tai-Jung Lin, Yao-Wen Chang
2025	—	`conf`	Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine Learning. ASP-DAC Chao-Chi Lan, Chuan-Chi Su, Yuan-Hsiang Lu, Yao-Wen Chang
2025	A	`conf`	Semidefinite Programming-Based Decoupling Capacitor Placement for Power Distribution Network Optimization. ICCAD Zong-Ying Cai, Wei-Han Mao, Yao-Wen Chang, Yang Lu, Jerry Bai, Bin-Chyi Tseng
2024	J	`jnl`	A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits. ACM Trans. Design Autom. Electr. Syst. Wei-Hsiang Tseng, Yao-Wen Chang
2024	A	`conf`	Efficient High-Fidelity Two-Dimensional Warpage Modeling for Advanced Packaging Analysis. ICCAD Shao-Yu Lo, MaoZe Liu, Yao-Wen Chang
2024	A	`conf`	Electrostatics-Based Analytical Global Placement for Timing Optimization. DATE Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao-Wen Chang
2024	J	`jnl`	High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, Yao-Wen Chang
2024	A*	`conf`	Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints. DAC Chien-Hao Tsou, Sheng-Yah Lin, Wei-Chen Hung, Yao-Wen Chang
2024	A*	`conf`	Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards. DAC Wei-Che Tseng, Zong-Ying Cai, Yi-Ping Huang, Yu-Hsiang Lo, Yao-Wen Chang
2024	A*	`conf`	Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes. DAC Yan-Jen Chen, Cheng-Hsiu Hsieh, Po-Han Su, Shao-Hsiang Chen, Yao-Wen Chang
2024	—	`conf`	Physical Design Challenges in Modern Heterogeneous Integration. ISPD Yao-Wen Chang
2024	A*	`conf`	Redistribution Layer Routing with Dynamic Via Insertion Under Irregular Via Structures. DAC Je-Wei Chuang, Zong-Han Wu, Bo-Ying Huang, Yao-Wen Chang
2024	—	`conf`	Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems. ISPD Wei-Hsiang Tseng, Yao-Wen Chang, Jie-Hong Roland Jiang
2024	J	`jnl`	Subgraph matching-based reference placement for printed circuit board designs. J. Supercomput. Ziran Zhu, Yilin Li, Miaodi Su, Shu Zhang, Haiyuan Su, Yifeng Xiao, Huan He, Jianli Chen, Yao-Wen Chang
2023	A	`conf`	A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs. ICCAD Yan-Lin Chen, Wei-Che Tseng, Wei-Yao Kao, Yao-Wen Chang
2023	A*	`conf`	A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints. DAC Qinghai Liu, Disi Lin, Chuandong Chen, Huan He, Jianli Chen, Yao-Wen Chang
2023	J	`jnl`	Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. ACM Trans. Design Autom. Electr. Syst. Min Wei, Xingyu Tong, Yuan Wen, Jianli Chen, Jun Yu, Wenxing Zhu, Yao-Wen Chang
2023	J	`jnl`	Analytical Solution of Poisson's Equation with Application to VLSI Global Placement. CoRR Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang
2023	A*	`conf`	Any-Angle Routing for Redistribution Layers in 2.5D IC Packages. DAC Min-Hsuan Chung, Je-Wei Chuang, Yao-Wen Chang
2023	A*	`conf`	Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints. DAC Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang
2023	A	`conf`	Floorplanning for Embedded Multi-Die Interconnect Bridge Packages. ICCAD Chung-Chia Lee, Yao-Wen Chang
2023	A*	`conf`	Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology. DAC Wei-Hsu Chen, Yao-Wen Chang
2023	A*	`conf`	Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits. DAC Wei-Hsiang Tseng, Yao-Wen Chang
2023	A*	`conf`	Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies. DAC Yan-Jen Chen, Yan-Syuan Chen, Wei-Che Tseng, Cheng-Yu Chiang, Yu-Hsiang Lo, Yao-Wen Chang
2023	A*	`conf`	PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration. DAC Zhijie Cai, Peng Zou, Zhengtao Wu, Xingyu Tong, Jun Yu, Jianli Chen, Yao-Wen Chang
2023	J	`jnl`	Routability-driven Power/Ground Network Optimization Based on Machine Learning. ACM Trans. Design Autom. Electr. Syst. Ping-Wei Huang, Yao-Wen Chang
2023	—	`conf`	Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks. ISPD Jhih-Wei Hsu, Kuan-Cheng Chen, Yan-Syuan Chen, Yu-Hsiang Lo, Yao-Wen Chang
2023	A*	`conf`	Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs. DAC Kuan-Cheng Chen, Yan-Lin Chen, Yu-Sheng Lu, Yao-Wen Chang
2023	J	`jnl`	What attracts young talent from Taiwan to start businesses in mainland China? A fuzzy analytic hierarchy process study. Technol. Anal. Strateg. Manag. Yao-Wen Chang, Yi-Hsuan Lai
2022	J	`jnl`	A Bridge-Based Compression Algorithm for Topological Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei-Hsiang Tseng, Chen-Hao Hsu, Wan-Hsuan Lin, Yao-Wen Chang
2022	A*	`conf`	A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits. DAC Wei-Hsiang Tseng, Yao-Wen Chang
2022	A*	`conf`	CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. DAC Huimin Wang, Xingyu Tong, Chenyue Ma, Runming Shi, Jianli Chen, Kun Wang, Jun Yu, Yao-Wen Chang
2022	J	`jnl`	Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2022	A*	`conf`	Flexible chip placement via reinforcement learning: late breaking results. DAC Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2022	—	`conf`	High-Correlation 3D Routability Estimation for Congestion-guided Global Routing. ASP-DAC Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang
2022	A*	`conf`	High-performance placement for large-scale heterogeneous FPGAs with clock constraints. DAC Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang
2022	—	`conf`	Intelligent Design Automation for Heterogeneous Integration. ISPD Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen
2022	J	`jnl`	Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianli Chen, Zhifeng Lin, Yanyue Xie, Wenxing Zhu, Yao-Wen Chang
2022	J	`jnl`	Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianli Chen, Ziran Zhu, Longkun Guo, Yu-Wei Tseng, Yao-Wen Chang
2022	J	`jnl`	Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianli Chen, Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu, Yao-Wen Chang
2022	A	`conf`	Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures. ICCAD Yen-Ting Chen, Yao-Wen Chang
2022	J	`jnl`	On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang
2022	A	`conf`	SGIRR: Sparse Graph Index Remapping for ReRAM Crossbar Operation Unit and Power Optimization. ICCAD Cheng-Yuan Wang, Yao-Wen Chang, Yuan-Hao Chang
2022	A*	`conf`	Subgraph matching based reference placement for PCB designs: late breaking results. DAC Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang
2022	A*	`conf`	Thermal-aware optical-electrical routing codesign for on-chip signal communications. DAC Yu-Sheng Lu, Kuan-Cheng Chen, Yu-Ling Hsu, Yao-Wen Chang
2022	J	`jnl`	Timing-Aware Fill Insertions With Design-Rule and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Yu, Wenxing Zhu, Yao-Wen Chang
2022	J	`jnl`	Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Sheng Lu, Yan-Lin Chen, Sheng-Jung Yu, Yao-Wen Chang
2022	A	`conf`	Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs. ICCAD Yang Hsu, Min-Hsuan Chung, Yao-Wen Chang, Ci-Hong Lin
2022	J	`jnl`	Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang
2022	—	`conf`	Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. ASP-DAC Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang
2022	A*	`conf`	Y-architecture-based flip-chip routing with dynamic programming-based bend minimization. DAC Szu-Ru Nie, Yen-Ting Chen, Yao-Wen Chang
2021	A*	`conf`	A Bridge-based Compression Algorithm for Topological Quantum Circuits. DAC Chen-Hao Hsu, Wan-Hsuan Lin, Wei-Hsiang Tseng, Yao-Wen Chang
2021	J	`jnl`	A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang
2021	J	`jnl`	A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization. ACM Trans. Design Autom. Electr. Syst. Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang
2021	A	`conf`	A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement. ICCAD Zih-Yao Lin, Yao-Wen Chang
2021	J	`jnl`	Analytical Placement Considering the Electron-Beam Fogging Effect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianli Chen, Yao-Wen Chang, Yu-Chen Huang
2021	A*	`conf`	Design and implementation of a generic 5G user plane function development framework. MobiCom Cheng-Ying Hsieh, Yao-Wen Chang, Chien Chen, Jyh-Cheng Chen
2021	J	`jnl`	Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianli Chen, Yao-Wen Chang, Yen-Yi Wu
2021	A	`conf`	On-chip Optical Routing with Waveguide Matching Constraints. ICCAD Fu-Yu Chuang, Yao-Wen Chang
2021	—	`conf`	Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
2021	A*	`conf`	Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems. DAC Ming-Hung Chen, Yao-Wen Chang, Junjie Wang
2021	A*	`conf`	Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias. DAC Yu-Jie Cai, Yang Hsu, Yao-Wen Chang
2021	A	`conf`	Time-Division Multiplexing Based System-Level FPGA Routing. ICCAD Wei-Kai Liu, Ming-Hung Chen, Chia-Ming Chang, Chen-Chia Chang, Yao-Wen Chang
2021	A	`conf`	Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. DATE Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang
2021	A*	`conf`	Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection. DAC Bingshu Wang, Lanfan Jiang, Wenxing Zhu, Longkun Guo, Jianli Chen, Yao-Wen Chang
2021	A*	`conf`	VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. DAC Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen
2020	A*	`conf`	A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. DAC Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang
2020	A*	`conf`	An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells DAC Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang
2020	J	`jnl`	Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo
2020	A*	`conf`	Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. DAC Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang
2020	A	`conf`	Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
2020	A*	`conf`	Latch Clustering for Timing-Power Co-Optimization. DAC Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang
2020	J	`jnl`	Mixed-Cell-Height Legalization Considering Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ziran Zhu, Jianli Chen, Wenxing Zhu, Yao-Wen Chang
2020	A	`conf`	Routability-Aware Pin Access Optimization for Monolithic 3D Designs. ICCAD Run-Yi Wang, Yao-Wen Chang
2020	—	`conf`	Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. IRPS Chieh Roger Lo, Teng-Hao Yeh, Wei-Chen Chen, Hang-Ting Lue, Keh-Chung Wang, Chih-Yuan Lu, Yao-Wen Chang, Yung-Hsiang Chen, Chu-Yung Liu
2020	A*	`conf`	Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. DAC Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang
2020	A*	`conf`	Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. DAC Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang
2020	—	`conf`	Unified Redistribution Layer Routing for 2.5D IC Packages. ASP-DAC Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang
2020	A*	`conf`	Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures. DAC Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang
2019	A*	`conf`	A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. DAC Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang
2019	—	`conf`	Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization. ISPD Xingquan Li, Jianli Chen, Wenxing Zhu, Yao-Wen Chang
2019	A	`conf`	Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. ICCAD Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang
2019	A*	`conf`	BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. DAC Fan-Keng Sun, Yao-Wen Chang
2019	J	`jnl`	DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Hsuan Su, Yao-Wen Chang
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	A	`conf`	Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly. ICCAD Zhan-Ling Wang, Yao-Wen Chang
2019	—	`conf`	MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. ASP-DAC Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo
2019	J	`jnl`	Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging. J. Digit. Imaging Dar-Ren Chen, Yao-Wen Chang, Hwa-Koon Wu, Wei-Chung Shia, Yu-Len Huang
2019	A	`conf`	Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs. ICCAD Yu-Hsuan Chang, Hsiang-Ting Wen, Yao-Wen Chang
2019	A	`conf`	Timing-Aware Fill Insertions with Design-Rule and Density Constraints. ICCAD Tingshen Lan, Xingquan Li, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang
2018	A	`conf`	A multithreaded initial detailed routing algorithm considering global routing guides. ICCAD Fan-Keng Sun, Hao Chen, Ching-Yu Chen, Chen-Hao Hsu, Yao-Wen Chang
2018	A	`conf`	Analytical solution of Poisson's equation and its application to VLSI global placement. ICCAD Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang
2018	A*	`conf`	DSA-friendly detailed routing considering double patterning and DSA template assignments. DAC Hai-Juan Yu, Yao-Wen Chang
2018	A*	`conf`	Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. DAC Run-Yi Wang, Chia-Cheng Pai, Junjie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang
2018	A*	`conf`	Generalized augmented lagrangian and its applications to VLSI global placement. DAC Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang
2018	A	`conf`	Mixed-cell-height legalization considering technology and region constraints. ICCAD Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang
2018	A	`conf`	Mixed-cell-height placement considering drain-to-drain abutment. ICCAD Yu-Wei Tseng, Yao-Wen Chang
2018	A	`conf`	Mixed-cell-height placement with complex minimum-implant-area constraints. ICCAD Jianli Chen, Peng Yang, Xingquan Li, Wenxing Zhu, Yao-Wen Chang
2018	J	`jnl`	NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany
2018	A	`conf`	Novel proximal group ADMM for placement considering fogging and proximity effects. ICCAD Jianli Chen, Li Yang, Zheng Peng, Wenxing Zhu, Yao-Wen Chang
2018	J	`jnl`	Provably Good Max-Min- IEEE Trans. Very Large Scale Integr. Syst. Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan
2018	A	`conf`	Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems. ICCAD Shih-Chun Chen, Richard Sun, Yao-Wen Chang
2018	A*	`conf`	WB-trees: a meshed tree representation for FinFET analog layout designs. DAC Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang
2017	A	`conf`	A novel damped-wave framework for macro placement. ICCAD Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen
2017	J	`jnl`	An Interview With Professor Chenming Hu, Father of 3D Transistors. IEEE Des. Test Yao-Wen Chang
2017	—	`conf`	An effective legalization algorithm for mixed-cell-height standard cells. ASP-DAC Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan
2017	A	`conf`	An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. ICCAD Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen
2017	A	`conf`	Blockage-aware terminal propagation for placement wirelength minimization. ICCAD Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen
2017	A	`conf`	Clock-aware placement for large-scale heterogeneous FPGAs. ICCAD Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo
2017	J	`jnl`	Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhi-Wen Lin, Yao-Wen Chang
2017	A*	`conf`	Detailed Placement for Two-Dimensional Directed Self-Assembly Technology. DAC Zhi-Wen Lin, Yao-Wen Chang
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	A	`conf`	FPGA placement and routing. ICCAD Shih-Chun Chen, Yao-Wen Chang
2017	A*	`conf`	Fogging Effect Aware Placement in Electron Beam Lithography. DAC Yu-Chen Huang, Yao-Wen Chang
2017	—	`conf`	Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement. ISPD Yao-Wen Chang
2017	A*	`conf`	Graph-Based Logic Bit Slicing for Datapath-Aware Placement. DAC Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang
2017	A	`conf`	Mixed-cell-height detailed placement considering complex minimum-implant-area constraints. ICCAD Yen-Yi Wu, Yao-Wen Chang
2017	J	`jnl`	Nanowire-Aware Routing Considering High Cut Mask Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Hsuan Su, Yao-Wen Chang
2017	A	`conf`	Redistribution layer routing for wafer-level integrated fan-out package-on-packages. ICCAD Ting-Chou Lin, Chia-Chih Chi, Yao-Wen Chang
2017	A*	`conf`	Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs. DAC Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang
2016	—	`conf`	Circular-contour-based obstacle-aware macro placement. ASP-DAC Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang
2016	—	`conf`	Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts. ASP-DAC Zhi-Wen Lin, Yao-Wen Chang
2016	A	`conf`	DSA-compliant routing for two-dimensional patterns using block copolymer lithography. ICCAD Yu-Hsuan Su, Yao-Wen Chang
2016	—	`conf`	Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs. ISPD Zhi-Wen Lin, Yao-Wen Chang
2016	J	`jnl`	Fast Lithographic Mask Optimization Considering Process Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang, Shayak Banerjee
2016	J	`jnl`	Layout-Dependent Effects-Aware Analytical Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang
2016	A*	`conf`	Minimum-implant-area-aware detailed placement with spacing constraints. DAC Kai-Han Tseng, Yao-Wen Chang, Charles C. C. Liu
2016	J	`jnl`	Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
2016	A*	`conf`	QB-trees: towards an optimal topological representation and its applications to analog layout designs. DAC I-Peng Wu, Hung-Chih Ou, Yao-Wen Chang
2016	—	`conf`	Recent research development and new challenges in analog layout synthesis. ASP-DAC Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung
2016	A	`conf`	Redistribution layer routing for integrated fan-out wafer-level chip-scale packages. ICCAD Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang
2016	J	`jnl`	Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang
2016	A*	`conf`	Timing-driven cell placement optimization for early slack histogram compression. DAC Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo
2016	A	`conf`	VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology. ICCAD Yu-Hsuan Su, Yao-Wen Chang
2015	J	`jnl`	Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao
2015	A*	`conf`	Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography. DAC Hung-Chih Ou, Kai-Han Tseng, Yao-Wen Chang
2015	A	`conf`	Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. ICCAD Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang
2015	—	`conf`	Detailed-Routing-Driven analytical standard-cell placement. ASP-DAC Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang
2015	A*	`conf`	EUV and e-beam manufacturability: challenges and solutions. DAC Yao-Wen Chang, Ru-Gun Liu, Shao-Yun Fang
2015	—	`conf`	Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. ASP-DAC Shao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang
2015	A*	`conf`	Layout-dependent-effects-aware analytical analog placement. DAC Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang
2015	A*	`conf`	Nanowire-aware routing considering high cut mask complexity. DAC Yu-Hsuan Su, Yao-Wen Chang
2015	—	`conf`	Non-stitch triple patterning-aware routing based on conflict graph pre-coloring. ASP-DAC Po-Ya Hsu, Yao-Wen Chang
2015	A	`conf`	Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. ICCAD Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan
2015	A*	`conf`	Routing-architecture-aware analytical placement for heterogeneous FPGAs. DAC Sheng-Yen Chen, Yao-Wen Chang
2015	J	`jnl`	Stitch-Aware Routing for Multiple E-Beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
2014	A*	`conf`	A New Asynchronous Pipeline Template for Power and Performance Optimization. DAC Kuan-Hsien Ho, Yao-Wen Chang
2014	J	`jnl`	A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen
2014	A	`conf`	Buffered clock tree synthesis considering self-heating effects. ISLPED Chung-Wei Lin, Tzu-Hsuan Hsu, Xin-Wei Shih, Yao-Wen Chang
2014	A	`conf`	Design and Implementation of a RESTful Notification Service. ICS Yao-Wen Chang, Ruey-Kai Sheu, Syuan-Ru Jhu, Yue-Shan Chang
2014	A	`conf`	Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs. ICCAD Yu-Chen Chen, Sheng-Yen Chen, Yao-Wen Chang
2014	A	`conf`	Fast lithographic mask optimization considering process variation. ICCAD Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang, Shayak Banerjee
2014	A*	`conf`	Functional ECO Using Metal-Configurable Gate-Array Spare Cells. DAC Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2014	J	`jnl`	NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang
2014	J	`jnl`	Nonuniform Multilevel Analog Routing With Matching Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang
2014	J	`jnl`	Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuan-Kai Ho, Hsu-Chieh Lee, Webber Lee, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen
2014	A*	`conf`	Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. DAC Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
2014	A*	`conf`	Routability-Driven Blockage-Aware Macro Placement. DAC Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang
2014	A*	`conf`	Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. DAC Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang
2014	C	`conf`	Simultaneous EUV flare- and CMP-aware placement. ICCD Chi-Yuan Liu, Yao-Wen Chang
2014	A	`ed.`	The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014 ICCAD Yao-Wen Chang
2013	A*	`conf`	An efficient and effective analytical placer for FPGAs. DAC Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang
2013	J	`jnl`	Circuit placement challenges: technical perspective. Commun. ACM Yao-Wen Chang
2013	A*	`conf`	Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. DAC Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao
2013	A*	`conf`	Double patterning lithography-aware analog placement. DAC Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang
2013	J	`jnl`	ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2013	J	`jnl`	Escape Routing for Staggered-Pin-Array PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang
2013	J	`jnl`	Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
2013	—	`conf`	Layer minimization in escape routing for staggered-pin-array PCBs. ASP-DAC Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng
2013	A*	`conf`	Multiple chip planning for chip-interposer codesign. DAC Yuan-Kai Ho, Yao-Wen Chang
2013	A*	`conf`	Routability-driven placement for hierarchical mixed-size circuit designs. DAC Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang
2013	—	`conf`	Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. ISPD Shao-Yun Fang, Chung-Wei Lin, Guang-Wan Liao, Yao-Wen Chang
2013	A*	`conf`	Simultaneous analog placement and routing with current flow and current density considerations. DAC Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang
2013	A*	`conf`	Stitch-aware routing for multiple e-beam lithography. DAC Shao-Yun Fang, Iou-Jen Liu, Yao-Wen Chang
2013	—	`conf`	Symmetrical buffered clock-tree synthesis with supply-voltage alignment. ASP-DAC Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao
2013	J	`jnl`	TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Meng-Kai Hsu, Valeriy Balabanov, Yao-Wen Chang
2012	A*	`conf`	A chip-package-board co-design methodology. DAC Hsu-Chieh Lee, Yao-Wen Chang
2012	A*	`conf`	A novel layout decomposition algorithm for triple patterning lithography. DAC Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen
2012	J	`jnl`	An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Wei Lin, Po-Wei Lee, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng
2012	J	`jnl`	Fast Timing-Model Independent Buffered Clock-Tree Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xin-Wei Shih, Yao-Wen Chang
2012	—	`conf`	Graph-based subfield scheduling for electron-beam photomask fabrication. ISPD Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
2012	J	`jnl`	Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang
2012	A*	`conf`	Non-uniform multilevel analog routing with matching constraints. DAC Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang
2012	A*	`conf`	Obstacle-avoiding free-assignment routing for flip-chip designs. DAC Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen
2012	A*	`conf`	Simultaneous flare level and flare variation minimization with dummification in EUVL. DAC Shao-Yun Fang, Yao-Wen Chang
2012	A	`conf`	Statistical thermal modeling and optimization considering leakage power variations. DATE Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang
2012	A*	`conf`	Structure-aware placement for datapath-intensive circuit designs. DAC Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang
2012	J	`jnl`	TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang
2012	J	`jnl`	Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2012	A*	`conf`	Timing ECO optimization using metal-configurable gate-array spare cells. DAC Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2012	J	`jnl`	Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Meng-Kai Hsu, Yao-Wen Chang
2011	—	`conf`	A SAT-based routing algorithm for cross-referencing biochips. SLIP Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang
2011	A	`conf`	A corner stitching compliant B ICCAD Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu
2011	J	`jnl`	Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cliff Chiung-Yu Lin, Yao-Wen Chang
2011	A	`conf`	Escape routing for staggered-pin-array PCBs. ICCAD Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang
2011	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, Yao-Wen Chang
2011	A	`conf`	Heterogeneous B ICCAD Pang-Yen Chou, Hung-Chih Ou, Yao-Wen Chang
2011	A	`conf`	PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. ICCAD Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu
2011	—	`ed.`	Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011 ISPD Yao-Wen Chang, Jiang Hu
2011	J	`jnl`	Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang
2011	A	`conf`	Routability-driven analytical placement for mixed-size circuit designs. ICCAD Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang
2011	J	`jnl`	Simultaneous Layout Migration and Decomposition for Double Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif
2011	A*	`conf`	Simultaneous functional and timing ECO. DAC Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2011	A*	`conf`	TSV-aware analytical placement for 3D IC designs. DAC Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov
2011	J	`jnl`	Thermal-Driven Analog Placement Considering Device Matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2011	A	`conf`	Timing ECO optimization via Bézier curve smoothing and fixability identification. ICCAD Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2011	J	`jnl`	Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang
2010	J	`jnl`	Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jia-Wei Fang, Yao-Wen Chang
2010	—	`conf`	Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. ASP-DAC Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang
2010	A*	`conf`	Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips. DAC Cliff Chiung-Yu Lin, Yao-Wen Chang
2010	—	`conf`	Density gradient minimization with coupling-constrained dummy fill for CMP control. ISPD Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang
2010	J	`jnl`	Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications. EURASIP J. Wirel. Commun. Netw. Jaw-Luen Tang, Yao-Wen Chang
2010	A	`conf`	Design-hierarchy aware mixed-size placement for routability optimization. ICCAD Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan
2010	J	`jnl`	ECO Timing Optimization Using Spare Cells and Technology Remapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang
2010	C	`conf`	Efficient provably good OPC modeling and its applications to interconnect optimization. ICCD Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang
2010	A*	`conf`	Fast timing-model independent buffered clock-tree synthesis. DAC Xin-Wei Shih, Yao-Wen Chang
2010	A	`conf`	High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. ICCAD Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang
2010	J	`jnl`	ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cliff Chiung-Yu Lin, Yao-Wen Chang
2010	J	`jnl`	Multilayer Global Routing With Via and Wire Capacity Considerations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
2010	A	`conf`	Native-conflict-aware wire perturbation for double patterning technology. ICCAD Szu-Yu Chen, Yao-Wen Chang
2010	J	`jnl`	Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang
2010	—	`ed.`	Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010 ISPD Prashant Saxena, Yao-Wen Chang
2010	A*	`conf`	Pulsed-latch aware placement for timing-integrity optimization. DAC Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang
2010	A	`conf`	Recent research development in flip-chip routing. ICCAD Hsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee
2010	A	`conf`	Redundant-wires-aware ECO timing and mask cost optimization. ICCAD Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang
2010	—	`conf`	TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang
2010	A	`conf`	Template-mask design methodology for double patterning technology. ICCAD Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif
2010	—	`conf`	Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. ASP-DAC Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang
2010	A	`conf`	Unified analytical global placement for large-scale mixed-size circuit designs. ICCAD Meng-Kai Hsu, Yao-Wen Chang
2009	J	`jnl`	A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang
2009	J	`jnl`	A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2009	J	`jnl`	An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang
2009	A	`conf`	An efficient pre-assignment routing algorithm for flip-chip designs. ICCAD Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng
2009	J	`jnl`	Analog Placement Based on Symmetry-Island Formulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark Po-Hung Lin, Yao-Wen Chang, Shyh-Chang Lin
2009	A	`conf`	BIST design optimization for large-scale embedded memory cores. ICCAD Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng
2009	J	`jnl`	Essential Issues in Analytical Placement Algorithms. Inf. Media Technol. Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen
2009	J	`jnl`	Essential Issues in Analytical Placement Algorithms. IPSJ Trans. Syst. LSI Des. Methodol. Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen
2009	A*	`conf`	Flip-chip routing with unified area-I/O pad assignments for package-board co-design. DAC Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
2009	—	`conf`	High-performance global routing with fast overflow reduction. ASP-DAC Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang
2009	A*	`conf`	ILP-based pin-count aware design methodology for microfluidic biochips. DAC Cliff Chiung-Yu Lin, Yao-Wen Chang
2009	—	`conf`	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. ISPD Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang
2009	A	`conf`	Simultaneous layout migration and decomposition for double patterning technology. ICCAD Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif
2009	A*	`conf`	Spare-cell-aware multilevel analytical placement. DAC Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao
2009	J	`jnl`	T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2009	A*	`conf`	Thermal-driven analog placement considering device matching. DAC Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2009	J	`jnl`	Voltage-Island Partitioning and Floorplanning Under Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
2009	A	`conf`	Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. ICCAD Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang
2008	—	`ed.`	2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008 FPT Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha
2008	J	`jnl`	A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
2008	A*	`conf`	A progressive-ILP based routing algorithm for cross-referencing biochips. DAC Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2008	J	`jnl`	An Efficient Graph-Based Algorithm for ESD Current Path Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen
2008	J	`jnl`	An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhe-Wei Jiang, Yao-Wen Chang
2008	A	`conf`	Area-I/O flip-chip routing for chip-package co-design. ICCAD Jia-Wei Fang, Yao-Wen Chang
2008	J	`jnl`	BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2008	A	`conf`	Constraint graph-based macro placement for modern mixed-size circuit designs. ICCAD Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang
2008	J	`jnl`	Effective Wire Models for X-Architecture Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
2008	J	`jnl`	Full-Chip Routing Considering Double-Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han
2008	—	`ch.`	Global Interconnect Planning. Handbook of Algorithms for Physical Design Automation Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang
2008	J	`jnl`	MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu
2008	J	`jnl`	Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
2008	—	`conf`	Metal-density driven placement for cmp variation and routability. ISPD Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
2008	A	`conf`	Multi-layer global routing considering via and wire capacities. ICCAD Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
2008	J	`jnl`	Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang
2008	J	`jnl`	NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2008	J	`jnl`	Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
2008	—	`ch.`	Packing Floorplan Representations. Handbook of Algorithms for Physical Design Automation Tung-Chieh Chen, Yao-Wen Chang
2008	A*	`conf`	Predictive formulae for OPC with applications to lithography-friendly routing. DAC Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang
2008	A*	`conf`	Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. DAC Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang
2008	A	`conf`	Routing for chip-package-board co-design considering differential pairs. ICCAD Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang
2007	A	`conf`	3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen
2007	J	`jnl`	A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang
2007	A*	`conf`	A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. DAC Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang
2007	—	`conf`	A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. PATMOS Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang
2007	J	`jnl`	An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bor-Yiing Su, Yao-Wen Chang, Jiang Hu
2007	A	`conf`	An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. ICCAD Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
2007	A*	`conf`	An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. DAC Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang
2007	J	`jnl`	An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bor-Yiing Su, Yao-Wen Chang
2007	A	`conf`	An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. ICCAD I-Jye Lin, Yao-Wen Chang
2007	A	`conf`	BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007	A	`conf`	ECO timing optimization using spare cells. ICCAD Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang
2007	A	`conf`	Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. ICCAD Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang
2007	—	`conf`	Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang
2007	—	`book`	Full-Chip Nanometer Routing Techniques. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
2007	J	`jnl`	MB IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang
2007	A*	`conf`	MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu
2007	J	`jnl`	Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tai-Chen Chen, Yao-Wen Chang
2007	J	`jnl`	Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007	—	`ch.`	NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. Modern Circuit Placement Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2007	A	`conf`	Novel wire density driven full-chip routing for CMP variation control. ICCAD Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang
2007	J	`jnl`	Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. ACM J. Emerg. Technol. Comput. Syst. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007	A	`conf`	Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007	J	`jnl`	Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen-Wei Liu, Yao-Wen Chang
2007	—	`conf`	Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang
2007	—	`conf`	Statistical circuit optimization considering device andinterconnect process variations. SLIP I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang
2007	J	`jnl`	Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007	—	`conf`	X-Route: An X-architecture full-chip multilevel router. SoCC Chen-Feng Chang, Yao-Wen Chang
2007	—	`conf`	X-architecture placement based on effective wire models. ISPD Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
2006	A	`conf`	A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2006	—	`conf`	A novel framework for multilevel full-chip gridless routing. ASP-DAC Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin
2006	—	`conf`	An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD Bor-Yiing Su, Yao-Wen Chang, Jiang Hu
2006	A	`conf`	An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. ICCAD Zhe-Wei Jiang, Yao-Wen Chang
2006	A	`conf`	Current path analysis for electrostatic discharge protection. ICCAD Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo
2006	—	`conf`	Floorplan and power/ground network co-synthesis for fast design convergence. ISPD Chen-Wei Liu, Yao-Wen Chang
2006	J	`jnl`	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
2006	—	`conf`	IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
2006	C	`conf`	Inductance extraction for general interconnect structures. ISCAS Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai
2006	J	`jnl`	Modern Floorplanning Based on B IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tung-Chieh Chen, Yao-Wen Chang
2006	J	`jnl`	Multilevel routing with jumper insertion for antenna avoidance. Integr. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
2006	—	`conf`	NTUplace2: a hybrid placer using partitioning and analytical techniques. ISPD Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2006	A*	`conf`	Novel full-chip gridless routing considering double-via insertion. DAC Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han
2006	A*	`conf`	Placement of digital microfluidic biochips using the t-tree formulation. DAC Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2006	J	`jnl`	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou
2006	J	`jnl`	Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
2006	—	`conf`	Simultaneous block and I/O buffer floorplanning for flip-chip design. ASP-DAC Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang
2006	A	`conf`	Voltage island aware floorplanning for power and timing optimization. ICCAD Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
2005	A	`conf`	A routing algorithm for flip-chip design. ICCAD Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang
2005	A*	`conf`	An exact jumper insertion algorithm for antenna effect avoidance/fixing. DAC Bor-Yiing Su, Yao-Wen Chang
2005	J	`jnl`	Crosstalk- and performance-driven multilevel full-chip routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee
2005	A	`conf`	IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
2005	A	`conf`	Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
2005	—	`conf`	Modern floorplanning based on fast simulated annealing. ISPD Tung-Chieh Chen, Yao-Wen Chang
2005	—	`conf`	Multilevel full-chip gridless routing considering optical proximity correction. ASP-DAC Tai-Chen Chen, Yao-Wen Chang
2005	A*	`conf`	Multilevel full-chip routing for the X-based architecture. DAC Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen
2005	—	`conf`	Multilevel full-chip routing with testability and yield enhancement. SLIP Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
2005	—	`conf`	NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. ISPD Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang
2005	—	`conf`	Placement with symmetry constraints for analog layout design using TCG-S. ASP-DAC Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang
2005	—	`conf`	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
2005	B	`conf`	Reconfigurable Platform for Content Science Research. RTCSA Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen
2005	—	`conf`	SoC test scheduling using the B-tree based floorplanning technique. ASP-DAC Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang
2005	J	`jnl`	TCG: A transitive closure graph-based representation for general floorplans. IEEE Trans. Very Large Scale Integr. Syst. Jai-Ming Lin, Yao-Wen Chang
2004	J	`jnl`	A clustering- and probability-based approach for time-multiplexed FPGA partitioning. Integr. Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang
2004	A*	`conf`	Efficient power/ground network analysis for power integrity-driven design methodology. DAC Su-Wei Wu, Yao-Wen Chang
2004	—	`conf`	Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. ASP-DAC Yi-Hui Cheng, Yao-Wen Chang
2004	—	`conf`	Layout techniques for on-chip interconnect inductance reduction. ASP-DAC Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
2004	J	`jnl`	MR: a new framework for multilevel full-chip routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yao-Wen Chang, Shih-Ping Lin
2004	—	`conf`	Multilevel routing with antenna avoidance. ISPD Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
2004	—	`conf`	Multilevel routing with jumper insertion for antenna avoidance. SoCC Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
2004	C	`conf`	Placement with Alignment and Performance Constraints Using the B*-Tree Representation. ICCD Meng-Chen Wu, Yao-Wen Chang
2004	—	`conf`	RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
2004	J	`jnl`	Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2004	J	`jnl`	TCG-S: orthogonal coupling of P IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jai-Ming Lin, Yao-Wen Chang
2004	—	`conf`	Temporal floorplanning using 3D-subTCG. ASP-DAC Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen
2004	A	`conf`	Temporal floorplanning using the T-tree formulation. ICCAD Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2004	J	`jnl`	Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integr. Syst. Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
2003	A	`conf`	A Fast Crosstalk- and Performance-Driven Multilevel Routing System. ICCAD Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee
2003	J	`jnl`	Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
2003	J	`jnl`	Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. Very Large Scale Integr. Syst. Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin
2003	—	`conf`	Graph matching-based algorithms for array-based FPGA segmentation design and routing. ASP-DAC Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang
2003	A*	`conf`	Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang
2003	—	`conf`	Noise-aware buffer planning for interconnect-driven floorplanning. ASP-DAC Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang
2003	J	`jnl`	Rectilinear block placement using B ACM Trans. Design Autom. Electr. Syst. Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang
2003	—	`conf`	Simultaneous floorplanning and buffer block planning. ASP-DAC Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2002	A	`conf`	A novel framework for multilevel routing considering routability and performance. ICCAD Shih-Ping Lin, Yao-Wen Chang
2002	J	`jnl`	Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. IEEE Trans. Very Large Scale Integr. Syst. Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
2002	A	`conf`	Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. DATE Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
2002	J	`jnl`	Comment on Generic Universal Switch Blocks. IEEE Trans. Computers Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang
2002	—	`conf`	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ISQED Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang
2002	J	`jnl`	Performance-driven placement for dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
2002	J	`jnl`	Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. VLSI Design Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong
2002	A*	`conf`	TCG-S: orthogonal coupling of P DAC Jai-Ming Lin, Yao-Wen Chang
2001	C	`conf`	An Algorithm for Dynamically Reconfigurable FPGA Placement. ICCD Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
2001	C	`conf`	Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
2001	J	`jnl`	Generic ILP-based approaches for time-multiplexed FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
2001	J	`jnl`	Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong
2001	C	`conf`	Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. ICCD Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
2001	A*	`conf`	TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. DAC Jai-Ming Lin, Yao-Wen Chang
2000	A*	`conf`	An architecture-driven metric for simultaneous placement and global routing for FPGAs. DAC Yao-Wen Chang, Yu-Tsang Chang
2000	A*	`conf`	B*-Trees: a new representation for non-slicing floorplans. DAC Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu
2000	C	`conf`	Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. ICCD Song-Ra Pan, Yao-Wen Chang
2000	J	`jnl`	Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
2000	J	`jnl`	Generic Universal Switch Blocks. IEEE Trans. Computers Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang
2000	—	`conf`	Optimal reliable crosstalk-driven interconnect optimization. ISPD Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
2000	C	`conf`	Rectilinear Block Placement Using B*-Trees. ICCD Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang
2000	J	`jnl`	Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, Kai Zhu, D. F. Wong
1999	A	`conf`	A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
1999	C	`conf`	Generic Universal Switch Blocks. ICCD Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang
1999	A*	`conf`	Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
1999	J	`jnl`	Quasi-Universal Switch Matrices for FPD Design. IEEE Trans. Computers Guang-Ming Wu, Yao-Wen Chang
1999	A	`conf`	Universal Switch Blocks for Three-Dimensional FPGA Design. FPGA Guang-Ming Wu, Michael Shyu, Yao-Wen Chang
1998	A	`conf`	Graph matching-based algorithms for FPGA segmentation design. ICCAD Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
1998	—	`conf`	Switch-matrix architecture and routing for FPDs. ISPD Guang-Ming Wu, Yao-Wen Chang
1998	C	`conf`	Timing-driven routing for symmetrical-array-based FPGAs. ICCD Kai Zhu, Yao-Wen Chang, D. F. Wong
1997	J	`jnl`	Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan
1996	A*	`conf`	Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC Chung-Ping Chen, Yao-Wen Chang, D. F. Wong
1996	A	`conf`	Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA Yao-Wen Chang, D. F. Wong, C. K. Wong
1996	J	`jnl`	Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, D. F. Wong, C. K. Wong
1995	C	`conf`	Design and analysis of FPGA/FPIC switch modules. ICCD Yao-Wen Chang, D. F. Wong, C. K. Wong
1995	C	`conf`	FPGA global routing based on a new congestion metric. ICCD Yao-Wen Chang, D. F. Wong, C. K. Wong
1994	A	`conf`	A new global routing algorithm for FPGAs. ICCAD Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
1993	A	`conf`	Switch module design with application to two-dimensional segmentation design. ICCAD Kai Zhu, D. F. Wong, Yao-Wen Chang