Yannick Bonhomme

21 papers A 6B 2C 2Misc 1Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2013 J jnl
Memory Reliability Improvement Based on Maximized Error-Correcting Codes.
J. Electron. Test.
Valentin Gherman, Samuel Evain, Yannick Bonhomme
2013 A conf
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.
DATE
Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman
2012 B conf
Memory reliability improvements based on maximized error-correcting codes.
ETS
Valentin Gherman, Samuel Evain, Yannick Bonhomme
2011 A conf
Error prediction based on concurrent self-test and reduced slack time.
DATE
Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme
2011 C conf
Generalized parity-check matrices for SEC-DED codes with fixed parity.
IOLTS
Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme
2011 Misc conf
Programmable extended SEC-DED codes for memory errors.
VTS
Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme
2010 C conf
Programmable restricted SEC codes to mask permanent faults in semiconductor memories.
IOLTS
Samuel Evain, Yannick Bonhomme, Valentin Gherman
2009 A conf
System-level hardware-based protection of memories against soft-errors.
DATE
Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme
2009 — conf
Transaction-based modeling for large scale simulations of heterogeneous systems.
SimuTools
Richard Buchmann, Mickael Cartron, Yannick Bonhomme
2008 — conf
Power-On Controller for high lifetime wireless sensor nodes.
WSAN
Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme
2006 J jnl
A Gated Clock Scheme for Low Power Testing of Logic Cores.
J. Electron. Test.
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2005 J jnl
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.
J. Low Power Electron.
Patrick Girard, Yannick Bonhomme
2004 B conf
An efficient scan tree design for test time reduction.
ETS
Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard
2004 A conf
Design of Routing-Constrained Low Power Scan Chains.
DATE
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004 — conf
Design of Routing-Constrained Low Power Scan Chains.
DELTA
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004 J jnl
Power-Driven Routing-Constrained Scan Chain Design.
J. Electron. Test.
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2003 A conf
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
ITC
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2002 A conf
Power Driven Chaining of Flip-Flops in Scan Architectures.
ITC
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2002 — conf
Test Power: a Big Issue in Large SOC Designs.
DELTA
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001 — conf
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Asian Test Symposium
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001 — conf
A Gated Clock Scheme for Low Power Scan-Based BIST.
IOLTW
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch