Yannan Nellie Wu

14 papers A* 3A 1B 4Journal 5

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	LoopTree: Exploring the Fused-Layer Dataflow Accelerator Design Space. IEEE Trans. Circuits Syst. Artif. Intell. Michael Gilbert, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2024	J	`jnl`	LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space. CoRR Michael Gilbert, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2023	A*	`conf`	HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. MICRO Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2023	J	`jnl`	HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. CoRR Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2023	B	`conf`	LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. ISPASS Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2023	—	`—`	Systematic Modeling and Design of Sparse Deep Neural Network Accelerators Yannan Nellie Wu
2023	A*	`conf`	Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. MICRO Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2023	J	`jnl`	Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. CoRR Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2022	A*	`conf`	Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. MICRO Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2022	J	`jnl`	Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. CoRR Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2021	B	`conf`	Architecture-Level Energy Estimation for Heterogeneous Computing Systems. ISPASS Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze
2021	B	`conf`	Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. ISPASS Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2020	B	`conf`	An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. ISPASS Yannan Nellie Wu, Vivienne Sze, Joel S. Emer
2019	A	`conf`	Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. ICCAD Yannan Nellie Wu, Joel S. Emer, Vivienne Sze