Yang Su

21 papers Journal 14Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption.
IEEE Trans. Circuits Syst. II Express Briefs
Jianfei Wang, Chen Yang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Leibo Liu
2025 J jnl
A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianfei Wang, Chen Yang, Yishuo Meng, Fahong Zhang, Jia Hou, Siwei Xiang, Yang Su
2025 J jnl
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline.
IEEE Trans. Very Large Scale Integr. Syst.
Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang
2025 J jnl
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering.
IEEE Trans. Very Large Scale Integr. Syst.
Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang
2025 J jnl
An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang
2025 — conf
Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data.
ASP-DAC
Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang
2024 J jnl
A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su
2024 J jnl
A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su
2024 J jnl
A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography.
IEEE Trans. Circuits Syst. II Express Briefs
Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang
2024 — conf
Sitting Posture Recognition Based on the Computer's Camera.
CVIPPR
Songyin Zhao, Yang Su
2023 J jnl
TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Yang Su
2022 J jnl
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication.
IEEE Trans. Very Large Scale Integr. Syst.
Yang Su, Bai-Long Yang, Chen Yang, Zepeng Yang, Yi-Wei Liu
2022 J jnl
ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yang Su, Bai-Long Yang, Chen Yang, Songyin Zhao
2021 — conf
A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference.
ICECS
Chen Yang, Zepeng Yang, Jia Hou, Yang Su
2021 J jnl
High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor.
J. Ambient Intell. Humaniz. Comput.
Yang Su, Bai-Long Yang, Chen Yang, Jing-Yuan He
2020 — conf
A Survey of Personalized Recommendation Based on Machine Learning Algorithms.
EITCE
Luogeng Tian, Bailong Yang, Xinli Yin, Yang Su
2020 J jnl
FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption.
IEEE Access
Yang Su, Bailong Yang, Chen Yang, Luogeng Tian
2019 J jnl
A high security and efficiency protection of confidentiality and integrity for off-chip memory.
J. Ambient Intell. Humaniz. Comput.
Yang Su, Junwei Shen, Min-Qing Zhang
2009 — conf
Further Study on Proxy Authorization and Its Scheme.
Complex (2)
Xuanwu Zhou, Yang Su, Ping Wei
2008 — conf
Approach on Aspect-Oriented Software Reverse Engineering at Requirements Level.
CSSE (2)
Yang Su, Xuan-Wu Zhou, Min-Qing Zhang
2008 — conf
Research on Modeling Traversing Features in Concurrent Software System.
CSSE (2)
Yang Su, Xuan-Wu Zhou, Min-Qing Zhang