Yang Liu

48 papers A* 2C 3Journal 40Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
A multi-synaptic memristor-based neural network and its encryption application.
Microelectron. J.
Tianhao Mao, Baosen Wang, Haodong Sun, Yian Liu, Shuang Liu, Yang Liu
2026 J jnl
FlowFlash: An Efficient Dataflow Strategy for FlashAttention Execution on Systolic Arrays.
IEEE Comput. Archit. Lett.
Baosen Wang, Junjie Wang, Siyu Xiao, Yang Liu
2026 A* conf
I2E: Real-Time Image-to-Event Conversion for High-Performance Spiking Neural Networks.
AAAI
Ruichen Ma, Liwei Meng, Guanchao Qiao, Ning Ning, Yang Liu, Shaogang Hu
2025 J jnl
A Neuromorphic Transformer Architecture Enabling Hardware-Friendly Edge Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pujun Zhou, R. C. Ma, Y. C. Chen, Z. T. Liu, C. Y. Liu, Liwei Meng, Guanchao Qiao, Yang Liu, Qi Yu, Shaogang Hu
2025 J jnl
An Image Encryption Algorithm Based on HNN with Memristor.
Int. J. Bifurc. Chaos
Yian Liu, Hao Hu, Ya Gao, Shaogang Hu, Qi Yu, Tupei Chen, Yang Liu
2025 J jnl
I2E: Real-Time Image-to-Event Conversion for High-Performance Spiking Neural Networks.
CoRR
Ruichen Ma, Liwei Meng, Guanchao Qiao, Ning Ning, Yang Liu, Shaogang Hu
2025 J jnl
Realization of Precise Perforating Using Dynamic Threshold and Physical Plausibility Algorithm for Self-Locating Perforating in Oil and Gas Wells.
CoRR
Siyu Xiao, Guohui Ren, Tianhao Mao, Yuqiao Chen, YiAn Liu, Junjie Wang, Kai Tang, Xindi Zhao, Zhijian Yu, Shuang Liu, Tupei Chen, Yang Liu
2025 J jnl
Timestep-Parallel 4D Neuromorphic Computing Array Enabling High Computing Power Density and High Energy Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs
Pujun Zhou, Changhui Xiao, Liwei Meng, Qi Yu, Ning Ning, Yang Liu, Shaogang Hu, Guanchao Qiao
2024 A* conf
A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network.
CVPR
Ruichen Ma, Guanchao Qiao, Yian Liu, Liwei Meng, Ning Ning, Yang Liu, Shaogang Hu
2024 J jnl
A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network.
CoRR
Ruichen Ma, Guanchao Qiao, Yian Liu, Liwei Meng, Ning Ning, Yang Liu, Shaogang Hu
2024 J jnl
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.
IEEE J. Solid State Circuits
Junjie Wang, Teng Zhang, Shuang Liu, Yihe Liu, Yuancong Wu, Shaogang Hu, Tupei Chen, Yang Liu, Yuchao Yang, Ru Huang
2024 J jnl
Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network.
Microelectron. J.
Yihe Liu, Junjie Wang, Shuang Liu, Mingyuan Sun, Xiaoyang Zhang, Jingtao Zhou, Shiqin Yan, Ruicheng Pan, Hao Hu, Yang Liu
2024 J jnl
Floating-Point Approximation Enabling Cost-Effective and High-Precision Digital Implementation of FitzHugh-Nagumo Neural Networks.
IEEE Trans. Biomed. Circuits Syst.
Yue Zuo, Ning Ning, Guanchao Qiao, J. H. Wu, Junhan Bao, Xiaoyang Zhang, Jian Bai, F. H. Wu, Yang Liu, Qi Yu, Shaogang Hu
2024 J jnl
Fullerene-Inspired Efficient Neuromorphic Network-on-Chip Scheme.
IEEE Trans. Circuits Syst. II Express Briefs
Pujun Zhou, Qi Yu, M. Chen, Guanchao Qiao, Yue Zuo, Zhong Zhang, Yang Liu, Shaogang Hu
2024 C conf
Live Demonstration for Input-Sparsity-Aware RRAM Processing-in-Memory Chip.
ISCAS
Junjie Wang, Shuang Liu, Ruicheng Pan, Shiqin Yan, Yihe Liu, Yang Liu
2024 J jnl
Spatio-Temporal Fusion Spiking Neural Network for Frame-Based and Event-Based Camera Sensor Fusion.
IEEE Trans. Emerg. Top. Comput. Intell.
Guanchao Qiao, Ning Ning, Yue Zuo, Pujun Zhou, Mingliang Sun, Shaogang Hu, Qi Yu, Yang Liu
2023 — conf
A Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology.
CECCT
Yihe Liu, Junjie Wang, Shuang Liu, Mingyuan Sun, Kai Tang, Guohui Ren, Xindi Zhao, Mingliang Sun, Yang Liu
2023 J jnl
Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth.
IEEE Trans. Biomed. Circuits Syst.
Pujun Zhou, Yue Zuo, Guanchao Qiao, C. M. Zhang, Zhong Zhang, Liwei Meng, Qi Yu, Yang Liu, Shaogang Hu
2023 J jnl
An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning.
IEEE Trans. Biomed. Circuits Syst.
Shuang Liu, Junjie Wang, Jingtao Zhou, Shaogang Hu, Qi Yu, Tupei Chen, Yang Liu
2023 J jnl
An efficient pruning and fine-tuning method for deep spiking neural network.
Appl. Intell.
Liwei Meng, Guanchao Qiao, Xiaoyang Zhang, Jian Bai, Yue Zuo, Pujun Zhou, Yang Liu, Shaogang Hu
2023 — conf
FPGA-implemented Memristor-based Transient Chaotic Neural Network for AES Edge Encryption.
CECCT
Hongzhe Wang, Kunsong Liu, Yi'an Liu, Junjie Wang, Mingyuan Sun, Kai Tang, Guohui Ren, Xindi Zhao, Yang Liu
2023 J jnl
Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory.
Sensors
Hongzhe Wang, Junjie Wang, Hao Hu, Guo Li, Shaogang Hu, Qi Yu, Zhen Liu, Tupei Chen, Shijie Zhou, Yang Liu
2022 J jnl
2022 roadmap on neuromorphic devices and applications research in China.
Neuromorph. Comput. Eng.
Qing Wan, Changjin Wan, Huaqiang Wu, Yuchao Yang, Xiaohe Huang, Peng Zhou, Lin Chen, Tian-Yu Wang, Yi Li, Kanhao Xue, Yu-Hui He, Xiangshui Miao, Xi Li, Chenchen Xie, Houpeng Chen, Zhitang Song, Hong Wang, Yue Hao, Junyao Zhang, Jia Huang, Zheng Yu Ren, Li Qiang Zhu, Jianyu Du, Chen Ge, Yang Liu, Guanglong Ding, Ye Zhou, Su-Ting Han, Guosheng Wang, Xiao Yu, Bing Chen, Zhufei Chu, Lunyao Wang, Yinshui Xia, Chen Mu, Feng Lin, Chixiao Chen, Bojun Cheng, Yannan Xing, Weitao Zeng, Hong Chen, Lei Yu, Giacomo Indiveri, Ning Qiao
2022 J jnl
A Co-Designed Neuromorphic Chip With Compact (17.9K F
IEEE Trans. Biomed. Circuits Syst.
Shaogang Hu, Guanchao Qiao, X. K. Liu, Y. H. Liu, C. M. Zhang, Yue Zuo, Pujun Zhou, Yian Liu, Ning Ning, Qi Yu, Yang Liu
2021 J jnl
Design of a constant loop bandwidth phase-locked loop based on artificial neural network.
IEICE Electron. Express
Rui Guo, Yuancong Wu, Shaogang Hu, Qi Yu, Tupei Chen, Yang Liu
2020 J jnl
A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Jian Luo, Yang Liu, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Qi Yu
2020 J jnl
An energy-efficient deep convolutional neural networks coprocessor for multi-object detection.
Microelectron. J.
Yuancong Wu, Junjie Wang, Kun Qian, Yanchen Liu, Rui Guo, Shaogang Hu, Qi Yu, Tupei Chen, Yang Liu, Limei Rong
2020 J jnl
Application of Deep Compression Technique in Spiking Neural Network Chip.
IEEE Trans. Biomed. Circuits Syst.
Yanchen Liu, Kun Qian, Shaogang Hu, Kun An, Sheng Xu, Xitong Zhan, Junjie Wang, Rui Guo, Yuancong Wu, Tupei Chen, Qi Yu, Yang Liu
2020 J jnl
Design of AM Self-Capacitive Transparent Touch Panel Based on a-IGZO Thin-Film Transistors.
IEEE Access
Kejun Wu, Jun Zhang, Yuanbo Li, Xiangzhan Wang, Yang Liu, Qi Yu, Tupei Chen
2019 J jnl
A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters.
J. Circuits Syst. Comput.
Jian Luo, Jing Li, Shuangyi Wu, Ning Ning, Yang Liu
2019 C conf
A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC.
ISCAS
Jian Luo, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Yang Liu, Qi Yu
2019 J jnl
A Neuromorphic-Hardware Oriented Bio-Plausible Online-Learning Spiking Neural Network Model.
IEEE Access
Chunming Qiao, Shaogang Hu, Junjie Wang, C. M. Zhang, Tupei Chen, Ning Ning, Qi Yu, Yang Liu
2019 J jnl
Design of a Neural Network-Based VCO With High Linearity and Wide Tuning Range.
IEEE Access
Rui Guo, Kun Qian, Jinping Wei, Tupei Chen, Yanchen Liu, Deyu Kong, Junjie Wang, Yuancong Wu, Shaogang Hu, Qi Yu, Yang Liu
2019 J jnl
Implementation of a Low Noise Amplifier With Self-Recovery Capability.
IEEE Access
Yanchen Liu, Caizhi Zhang, Tupei Chen, Deyu Kong, Rui Guo, Junjie Wang, Yuancong Wu, Shaogang Hu, L. M. Rong, Qi Yu, Yang Liu
2019 J jnl
Study of Recall Time of Associative Memory in a Memristive Hopfield Neural Network.
IEEE Access
Deyu Kong, Shaogang Hu, Junjie Wang, Zhen Liu, Tupei Chen, Qi Yu, Yang Liu
2018 J jnl
A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu
2018 J jnl
Predicting House Price With a Memristor-Based Artificial Neural Network.
IEEE Access
Junjie Wang, Shaogang Hu, X. T. Zhan, Q. Luo, Qi Yu, Zhen Liu, Tupei Chen, Y. Yin, Sumio Hosaka, Yang Liu
2018 J jnl
Realization of a Power-Efficient Transmitter Based on Integrated Artificial Neural Network.
IEEE Access
Deyu Kong, Shaogang Hu, Yuancong Wu, Junjie Wang, Canlong Xiong, Qi Yu, Zhengyu Shi, Zhen Liu, Tupei Chen, You Yin, Sumio Hosaka, Yang Liu
2018 J jnl
The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction.
IEEE Access
Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu
2015 J jnl
A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors.
IEEE Trans. Very Large Scale Integr. Syst.
Zhentao Xu, Wei Wang, Ning Ning, Wei Meng Lim, Yang Liu, Qi Yu
2015 J jnl
Total ionizing dose sensitivity of function blocks in FRAM.
Microelectron. Reliab.
Ke Gu, Juin J. Liou, Wei Li, Yang Liu, Ping Li
2014 C conf
A 10-bit 100MS/s subrange SAR ADC with time-domain quantization.
ISCAS
Ling Du, Shuangyi Wu, Min Jiang, Ning Ning, Qi Yu, Yang Liu
2014 J jnl
A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. II Express Briefs
Jing Li, Shuangyi Wu, Yang Liu, Ning Ning, Qi Yu
2014 J jnl
A digital background calibration technique for SAR ADC based on capacitor swapping.
IEICE Electron. Express
Ling Du, Ning Ning, Shuangyi Wu, Qi Yu, Yang Liu
2014 J jnl
A dithering Technique for Sha_less Pipelined ADC.
J. Circuits Syst. Comput.
Ning Ning, Ling Du, Hua Chen, Shuangyi Wu, Qi Yu, Yang Liu
2014 J jnl
Digital Background Calibration for Timing skew in Time-Interleaved ADC.
J. Circuits Syst. Comput.
Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu
2013 — conf
A process variation insensitive bandgap reference with self-calibration technique.
ASICON
Ling Du, Ning Ning, Kejun Wu, Yang Liu, Qi Yu
2013 J jnl
Vco-Based continuous-Time Sigma Delta ADC Based on a Dual-VCO-quantizer-Loop Structure.
J. Circuits Syst. Comput.
Zhentao Xu, X. L. Zhang, J. Z. Chen, Shaogang Hu, Qi Yu, Yang Liu, Wei Meng Lim