Yang Hu - RankMe

141 papers A* 36A 8B 5C 3Journal 55Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	2.9 A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering. ISSCC Xiaolong Yang, Yang Wang, Wende Xu, Yubin Qin, Huanyu Wang, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2026	—	`conf`	A 28nm 47.3TFLOPs/W 894mJ/Inference Visual Autoregressive Accelerator with Differential-Amplifier Speculation and Chain-Reaction-Like Parallel Generation. ISSCC Zhiheng Yue, Xujiang Xiang, Jiamu Fu, Shaojun Wei, Yang Wang, Yang Hu, Shouyi Yin
2026	—	`conf`	A 28nm Speculative-Decoding LLM Processor Achieving 105-to-685µs/Token Latency for Billion-Parameter Models. ISSCC Yang Wang, Huanyu Wang, Jiaxin Yang, Yutong Su, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2026	—	`conf`	BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination. ASP-DAC Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2026	J	`jnl`	Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. IEEE Trans. Computers Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2026	J	`jnl`	ETCIM: Error-Tolerant Digital CIM Processor With Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction. IEEE J. Solid State Circuits Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2026	A*	`conf`	FACE: Fully Overlapped PD Scheduling and Multi-Level Architecture Co-Exploration on Wafer. HPCA Zheng Xu, Dehao Kong, Jiaxin Liu, Dingcheng Jiang, Xu Dai, Jinyi Deng, Yang Hu, Shouyi Yin
2026	A*	`conf`	HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture With Unified Low-Cost Iterative Error Correction. HPCA Zhen He, Yiqi Wang, Zhiheng Yue, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2026	—	`conf`	LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model. ASP-DAC Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2026	J	`jnl`	MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. Zhen He, Yiqi Wang, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Chao Li, Fengbin Tu, Shouyi Yin
2026	—	`conf`	MoBiLE: Efficient Mixture-of-Experts Inference on Consumer GPU with Mixture of Big Little Experts. ASP-DAC Yushu Zhao, Yubin Qin, Yang Wang, Xiaolong Yang, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2026	A*	`conf`	MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference. HPCA Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin
2026	A*	`conf`	Nearly Optimal Bounds for Stochastic Online Sorting. SODA Yang Hu
2026	A*	`conf`	PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion. HPCA Huizheng Wang, Hongbin Wang, Zichuan Wang, Zhiheng Yue, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2026	A*	`conf`	ReThermal: Co-Design of Thermal-Aware Static and Dynamic Scheduling for LLM Training on Liquid-Cooled Wafer-Scale Chips. HPCA Chengran Li, Huizheng Wang, Jiaxin Liu, Jingyao Liu, Zhiheng Yue, Xia Li, Shenfei Jiang, Jinyi Deng, Yang Hu, Shouyi Yin
2026	A*	`conf`	TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips. HPCA Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin
2026	A*	`conf`	WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip. HPCA Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin
2026	—	`conf`	XY-Serve: End-to-End Versatile Production Serving for Dynamic LLM Workloads. ASPLOS (1) Mingcong Song, Xinru Tang, Fengfan Hou, Jing Li, Wei Wei, Yipeng Ma, Runqiu Xiao, Hongjie Si, Dingcheng Jiang, Shouyi Yin, Yang Hu, Guoping Long
2025	—	`conf`	14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and < ISSCC Zhiheng Yue, Xujiang Xiang, Yang Wang, Ruiqi Guo, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	—	`conf`	23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation. ISSCC Yubin Qin, Yang Wang, Jiachen Wang, Zhiwei Lin, Yushu Zhao, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	3D-PATH: A Hierarchy LUT Processing-in-memory Accelerator with Thermal-aware Hybrid Bonding Integration. MICRO Zhiheng Yue, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications. IEEE J. Solid State Circuits Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	—	`conf`	AnalogAI: A Generalized Accuracy Recovery Framework for DNNs under Analog Computing. AICAS Yinghao Li, Jiaqi Lv, Xueling Wang, Xu Dai, Xufeng He, Lei Wang, Yiran Zhang, Xin Si, Yang Hu, Shouyi Yin
2025	J	`jnl`	BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination. IEEE Trans. Circuits Syst. II Express Briefs Huizheng Wang, Hongbin Wang, Zhiheng Yue, Jingyao Liu, Taiquan Wei, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training. IEEE Trans. Circuits Syst. II Express Briefs Yang Zhou, Yang Wang, Wenxin Yin, Yazheng Jiang, Jingchuan Wei, Yubin Qin, Yang Hu, Shaojun Wei, Shouyi Yin
2025	J	`jnl`	BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination. CoRR Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. IEEE J. Solid State Circuits Zhiheng Yue, Yang Wang, Huizheng Wang, Ruiqi Guo, Fengbin Tu, Jianxun Yang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip. ISCA Xingmao Yu, Dingcheng Jiang, Jinyi Deng, Jingyao Liu, Chao Li, Shouyi Yin, Yang Hu
2025	J	`jnl`	Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. CoRR Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap. Xujiang Xiang, Zhiheng Yue, Xiaolong Zhang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. HPCA Zhen He, Yiqi Wang, Zihan Wu, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2025	J	`jnl`	From Quarter to All: Accelerating Speculative LLM Decoding via Floating-Point Exponent Remapping and Parameter Sharing. CoRR Yushu Zhao, Yubin Qin, Yang Wang, Xiaolong Yang, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	HPCTransCompile: An AI Compiler Generated Dataset for High-Performance CUDA Transpilation and LLM Preliminary Exploration. CoRR Jiaqi Lv, Xufeng He, Yanchen Liu, Xu Dai, Yang Hu, Shouyi Yin
2025	J	`jnl`	LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model. CoRR Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. MICRO Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. CoRR Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MoBiLE: Efficient Mixture-of-Experts Inference on Consumer GPU with Mixture of Big Little Experts. CoRR Yushu Zhao, Yubin Qin, Yang Wang, Xiaolong Yang, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MoEntwine: Unleashing the Potential of Wafer-scale Chips for Large-scale Expert Parallel Inference. CoRR Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin
2025	J	`jnl`	PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion. CoRR Huizheng Wang, Hongbin Wang, Zichuan Wang, Zhiheng Yue, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2025	—	`conf`	PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture. ASAP Weiwei Wu, Fengbin Tu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin
2025	A*	`conf`	PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. ISCA Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu
2025	C	`conf`	RAM-Wafer: RL-Based Automatic Mapping Framework for Large-Scale AI Training on Wafer-Scale Computing. ICCD Xu Dai, Dehao Kong, Xufeng He, Zijun Xu, Shaopeng Zhai, Yang Hu, Shouyi Yin
2025	J	`jnl`	Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design. IEEE Trans. Computers Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2025	—	`conf`	Segmentation-Aware Optimization of Collective for Waferscale Chips. APPT Qize Yang, Jiaxin Liu, Taiquan Wei, Yuxin Jin, Shouyi Yin, Yang Hu
2025	—	`conf`	Spatial-Aware Orchestration of LLM Attention on Waferscale Chips. APPT Taiquan Wei, Huizheng Wang, Zichuan Wang, Shouyi Yin, Yang Hu
2025	J	`jnl`	TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips. CoRR Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin
2025	J	`jnl`	TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. IEEE J. Solid State Circuits Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Fengbin Tu, Shouyi Yin
2025	A*	`conf`	WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips. ISCA Zheng Xu, Dehao Kong, Jiaxin Liu, Jinxi Li, Jingxiang Hou, Xu Dai, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolution. CoRR Jinwu Chen, Qidie Wu, Bin Li, Lin Ma, Xin Si, Yang Hu, Shouyi Yin, Jun Yang
2024	—	`conf`	15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. ISSCC Zhiheng Yue, Xujiang Xiang, Fengbin Tu, Yang Wang, Yiming Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. ISSCC Ruiqi Guo, Lei Wang, Xiaofeng Chen, Hao Sun, Zhiheng Yue, Yubin Qin, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications. ISSCC Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. VLSI Technology and Circuits Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure. A-SSCC Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm VLSI Technology and Circuits Ruiqi Guo, Xiaofeng Chen, Lei Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication. VLSI Technology and Circuits Yubin Qin, Yang Wang, Xiaolong Yang, Zhiren Zhao, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things. ISCA Xiaofeng Hou, Tongqiao Xu, Chao Li, Cheng Xu, Jiacheng Liu, Yang Hu, Jieru Zhao, Jingwen Leng, Kwang-Ting Cheng, Minyi Guo
2024	J	`jnl`	Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow. IEEE J. Solid State Circuits Yubin Qin, Yang Wang, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Yang Zhou, Yuanqi Fan, Jingchuan Wei, Tianbao Chen, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A	`conf`	Boosting Data Center Performance via Intelligently Managed Multi-backend Disaggregated Memory. SC Jing Wang, Hanzhang Yang, Chao Li, Yiming Zhuansun, Wang Yuan, Cheng Xu, Xiaofeng Hou, Minyi Guo, Yang Hu, Yaqian Zhao
2024	A*	`conf`	CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. DAC Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2024	J	`jnl`	CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering. IEEE J. Solid State Circuits Ruiqi Guo, Xiaofeng Chen, Lei Wang, Yang Wang, Hao Sun, Jingchuan Wei, Huiming Han, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. DAC Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. VLSI Technology and Circuits Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2024	J	`jnl`	Efficient Orchestrated AI Workflows Execution on Scale-Out Spatial Architecture. IEEE Trans. Circuits Syst. Artif. Intell. Jinyi Deng, Xinru Tang, Zhiheng Yue, Guangyang Lu, Qize Yang, Jiahao Zhang, Jinxi Li, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2024	J	`jnl`	Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture. CoRR Jinyi Deng, Xinru Tang, Zhiheng Yue, Guangyang Lu, Qize Yang, Jiahao Zhang, Jinxi Li, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. ISCA Zhiheng Yue, Huizheng Wang, Jiahao Fang, Jinyi Deng, Guangyang Lu, Fengbin Tu, Ruiqi Guo, Yuxuan Li, Yubin Qin, Yang Wang, Chao Li, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing. DAC Xiaolong Yang, Yang Wang, Yubin Qin, Jiachen Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference. DAC Zheng Xu, Xu Dai, Shaojun Wei, Shouyi Yin, Yang Hu
2024	A*	`conf`	MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition. ISCA Yubin Qin, Yang Wang, Zhiren Zhao, Xiaolong Yang, Yang Zhou, Shaojun Wei, Yang Hu, Shouyi Yin
2024	J	`jnl`	MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. IEEE J. Solid State Circuits Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2024	J	`jnl`	Optimizing the Micro-Architectural Performance of the Current and Emerging Edge Infrastructure. IEEE Trans. Cloud Comput. Jianda Wang, Zhen Wang, Weili Wu, Yang Hu
2024	J	`jnl`	PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training. CoRR Jiahao Fang, Huizheng Wang, Qize Yang, Dehao Kong, Xu Dai, Jinyi Deng, Yang Hu, Shouyi Yin
2024	A*	`conf`	SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. MICRO Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qinze Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2024	J	`jnl`	SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. CoRR Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qize Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2024	J	`jnl`	Tackling the Dynamicity in a Production LLM Serving System with SOTA Optimizations via Hybrid Prefill/Decode/Verify Scheduling on Efficient Meta-kernels. CoRR Mingcong Song, Xinru Tang, Fengfan Hou, Jing Li, Wei Wei, Yipeng Ma, Runqiu Xiao, Hongjie Si, Dingcheng Jiang, Shouyi Yin, Yang Hu, Guoping Long
2023	—	`conf`	A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination. A-SSCC Yubin Qin, Yang Wang, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Yang Zhou, Yuanqi Fan, Jingchuan Wei, Tianbao Chen, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	—	`conf`	A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing. VLSI Technology and Circuits Yang Wang, Yubin Qin, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	—	`conf`	A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions. AICAS Xiaofeng Chen, Ruiqi Guo, Zhiheng Yue, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2023	—	`conf`	CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering. A-SSCC Ruiqi Guo, Yang Wang, Xiaofeng Chen, Lei Wang, Hao Sun, Jingchuan Wei, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	—	`conf`	CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. ISSCC Zhiheng Yue, Yang Wang, Huizheng Wang, Yabing Wang, Ruiqi Guo, Limei Tang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	Catch-Up Distillation: You Only Need to Train Once for Accelerating Sampling. CoRR Shitong Shao, Xu Dai, Shouyi Yin, Lujun Li, Huanran Chen, Yang Hu
2023	J	`jnl`	Data Fusion in Infrastructure-Augmented Autonomous Driving System: Why? Where? and How? IEEE Internet Things J. Jianda Wang, Zhendong Wang, Bo Yu, Jie Tang, Shuaiwen Leon Song, Cong Liu, Yang Hu
2023	A*	`conf`	FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction. ISCA Yubin Qin, Yang Wang, Dazheng Deng, Zhiren Zhao, Xiaolong Yang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	—	`conf`	MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. ISSCC Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2023	A*	`conf`	RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. DAC Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2023	J	`jnl`	STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. Weiwei Wu, Fengbin Tu, Mengqi Niu, Zhiheng Yue, Leibo Liu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin
2023	—	`conf`	TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. ISSCC Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2023	A*	`conf`	Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. MICRO Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Boxiao Han, Hongjun He, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. CoRR Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	Towards an Efficient SIMD Virtual Radio Access Network (vRAN) and Edge Cloud System. IEEE Trans. Cloud Comput. Jianda Wang, Zhen Wang, Yang Hu
2023	J	`jnl`	Wafer-scale Computing: Advancements, Challenges, and Future Perspectives. CoRR Yang Hu, Xinhan Lin, Huizheng Wang, Zhen He, Xingmao Yu, Jiahao Zhang, Qize Yang, Zheng Xu, Sihan Guan, Jiahao Fang, Haoran Shang, Xinru Tang, Xu Dai, Shaojun Wei, Shouyi Yin
2023	J	`jnl`	WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. CoRR Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	A synergistic reinforcement learning-based framework design in driving automation. Comput. Electr. Eng. Yuqiong Qi, Yang Hu, Haibin Wu, Shen Li, Xiaochun Ye, Dongrui Fan
2022	A	`conf`	Brief Industry Paper: The Necessity of Adaptive Data Fusion in Infrastructure-Augmented Autonomous Driving System. RTAS Shaoshan Liu, Jianda Wang, Zhendong Wang, Bo Yu, Wei Hu, Yahui Liu, Jie Tang, Shuaiwen Leon Song, Cong Liu, Yang Hu
2022	J	`jnl`	Brief Industry Paper: The Necessity of Adaptive Data Fusion in Infrastructure-Augmented Autonomous Driving System. CoRR Shaoshan Liu, Jianda Wang, Zhendong Wang, Bo Yu, Wei Hu, Yahui Liu, Jie Tang, Shuaiwen Leon Song, Cong Liu, Yang Hu
2022	J	`jnl`	Demystifying Arch-hints for Model Extraction: An Attack in Unified Memory System. CoRR Zhendong Wang, Xiaoming Zeng, Xulong Tang, Danfeng Zhang, Xing Hu, Yang Hu
2022	J	`jnl`	Enabling Efficient Deep Convolutional Neural Network-based Sensor Fusion for Autonomous Driving. CoRR Xiaoming Zeng, Zhendong Wang, Yang Hu
2022	A*	`conf`	Enabling efficient deep convolutional neural network-based sensor fusion for autonomous driving. DAC Xiaoming Zeng, Zhendong Wang, Yang Hu
2022	J	`jnl`	Towards Efficient Architecture and Algorithms for Sensor Fusion. CoRR Zhendong Wang, Xiaoming Zeng, Shuaiwen Leon Song, Yang Hu
2022	J	`jnl`	Towards a High-performance and Secure Memory System and Architecture for Emerging Applications. CoRR Zhendong Wang, Yang Hu
2021	—	`conf`	Characterization and Implication of Edge WebAssembly Runtimes. HPCC/DSS/SmartCity/DependSys Zhen Wang, Jianda Wang, Zhendong Wang, Yang Hu
2021	B	`conf`	Enabling Efficient SIMD Acceleration for Virtual Radio Access Network. ICPP Jianda Wang, Yang Hu
2021	J	`jnl`	Q-VR: System-Level Design for Future Mobile Collaborative Virtual Reality. CoRR Chenhao Xie, Xie Li, Yang Hu, Huwan Peng, Michael B. Taylor, Shuaiwen Leon Song
2021	A*	`conf`	Q-VR: system-level design for future mobile collaborative virtual reality. ASPLOS Chenhao Xie, Xie Li, Yang Hu, Huwan Peng, Michael B. Taylor, Shuaiwen Leon Song
2021	J	`jnl`	Tackling Variabilities in Autonomous Driving. CoRR Yuqiong Qi, Yang Hu, Haibin Wu, Shen Li, Haiyu Mao, Xiaochun Ye, Dongrui Fan, Ninghui Sun
2021	—	`conf`	Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption. ATS Zhendong Wang, Rujia Wang, Zihang Jiang, Xulong Tang, Shouyi Yin, Yang Hu
2020	J	`jnl`	A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics. IEEE Trans. Computers Liwei Zhou, Yang Hu, Yiorgos Makris
2020	A	`conf`	ANT-man: towards agile power management in the microservice era. SC Xiaofeng Hou, Chao Li, Jiacheng Liu, Lu Zhang, Yang Hu, Minyi Guo
2020	A	`conf`	Co-Optimizing Performance and Memory Footprint Via Integrated CPU/GPU Memory Management, an Implementation on Autonomous Driving Platform. RTAS Soroush Bateni, Zhendong Wang, Yuankun Zhu, Yang Hu, Cong Liu
2020	J	`jnl`	Co-Optimizing Performance and Memory FootprintVia Integrated CPU/GPU Memory Management, anImplementation on Autonomous Driving Platform. CoRR Soroush Bateni, Zhendong Wang, Yuankun Zhu, Yang Hu, Cong Liu
2020	J	`jnl`	Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhendong Wang, Zihang Jiang, Zhen Wang, Xulong Tang, Cong Liu, Shouyi Yin, Yang Hu
2020	B	`conf`	Performance Analysis of 5G NR vRAN Platform and its Implications on Edge Computing. ISPASS Jianda Wang, Yang Hu
2020	—	`conf`	Understanding and Tackling the Hidden Memory Latency for Edge-based Heterogeneous Platform. HotEdge Zhendong Wang, Zhen Wang, Cong Liu, Yang Hu
2019	C	`conf`	An FPGA Implementation of Stochastic Computing-Based LSTM. ICCD Guy Maor, Xiaoming Zeng, Zhendong Wang, Yang Hu
2019	C	`conf`	Architectural and Cost Implications of the 5G Edge NFV Systems. ICCD Yang Hu, Jianda Wang
2019	—	`conf`	Characterizing and Understanding the Architectural Implications of Cloudnative Edge NFV Workloads. NFV-SDN Jianda Wang, Yang Hu
2019	B	`conf`	Characterizing and orchestrating NFV-ready servers for efficient edge data processing. IWQoS Lu Zhang, Chao Li, Pengyu Wang, Yunxin Liu, Yang Hu, Quan Chen, Minyi Guo
2018	J	`jnl`	A Flattened Metadata Service for Distributed File Systems. IEEE Trans. Parallel Distributed Syst. Siyang Li, Fenlin Liu, Jiwu Shu, Youyou Lu, Tao Li, Yang Hu
2018	A*	`conf`	Enabling Efficient Network Service Function Chain Deployment on Heterogeneous Server Platform. HPCA Yang Hu, Tao Li
2018	J	`jnl`	Exploring Customizable Heterogeneous Power Distribution and Management for Datacenter. IEEE Trans. Parallel Distributed Syst. Longjun Liu, Hongbin Sun, Chao Li, Yang Hu, Tao Li, Nanning Zheng
2018	A*	`conf`	In-Situ AI: Towards Autonomous and Incremental Deep Learning for IoT Systems. HPCA Mingcong Song, Kan Zhong, Jiaqi Zhang, Yang Hu, Duo Liu, Weigong Zhang, Jing Wang, Tao Li
2018	A*	`conf`	Prediction Based Execution on Deep Neural Networks. ISCA Mingcong Song, Jiechen Zhao, Yang Hu, Jiaqi Zhang, Tao Li
2017	B	`conf`	GaaS workload characterization under NUMA architecture for virtualized GPU. ISPASS Huixiang Chen, Meng Wang, Yang Hu, Mingcong Song, Tao Li
2017	A	`conf`	LocoFS: a loosely-coupled metadata service for distributed file systems. SC Siyang Li, Youyou Lu, Jiwu Shu, Yang Hu, Tao Li
2017	J	`jnl`	Oasis: Scaling Out Datacenter Sustainably and Economically. IEEE Trans. Parallel Distributed Syst. Chao Li, Yang Hu, Juncheng Gu, Jingling Yuan, Tao Li
2017	A*	`conf`	Towards "Full Containerization" in Containerized Network Function Virtualization. ASPLOS Yang Hu, Mingcong Song, Tao Li
2017	A*	`conf`	Towards Pervasive and User Satisfactory CNN across GPU Microarchitectures. HPCA Mingcong Song, Yang Hu, Huixiang Chen, Tao Li
2016	B	`conf`	Bridging the Semantic Gaps of GPU Acceleration for Scale-out CNN-based Big Data Processing: Think Big, See Small. PACT Mingcong Song, Yang Hu, Yunlong Xu, Chao Li, Huixiang Chen, Jingling Yuan, Tao Li
2016	A	`conf`	HOPE: Enabling Efficient Service Orchestration in Software-Defined Data Centers. ICS Yang Hu, Chao Li, Longjun Liu, Tao Li
2016	J	`jnl`	RE-UPS: an adaptive distributed energy storage system for dynamically managing solar energy in green datacenters. J. Supercomput. Longjun Liu, Hongbin Sun, Chao Li, Yang Hu, Jingmin Xin, Nanning Zheng, Tao Li
2016	A	`conf`	Towards an Adaptive Multi-Power-Source Datacenter. ICS Longjun Liu, Hongbin Sun, Chao Li, Yang Hu, Nanning Zheng, Tao Li
2016	A*	`conf`	Towards efficient server architecture for virtualized network function deployment: Implications and implementations. MICRO Yang Hu, Tao Li
2015	A	`conf`	BAAT: Towards Dynamically Managing Battery Aging in Green Datacenters. DSN Longjun Liu, Chao Li, Hongbin Sun, Yang Hu, Juncheng Gu, Tao Li
2015	A*	`conf`	HEB: deploying and managing hybrid energy buffers for improving datacenter efficiency and economy. ISCA Longjun Liu, Chao Li, Hongbin Sun, Yang Hu, Juncheng Gu, Tao Li, Jingmin Xin, Nanning Zheng
2015	J	`jnl`	Leveraging Heterogeneous Power for Improving Datacenter Efficiency and Resiliency. IEEE Comput. Archit. Lett. Longjun Liu, Chao Li, Hongbin Sun, Yang Hu, Jingmin Xin, Nanning Zheng, Tao Li
2015	A*	`conf`	Towards sustainable in-situ server systems in the big data era. ISCA Chao Li, Yang Hu, Longjun Liu, Juncheng Gu, Mingcong Song, Xiaoyao Liang, Jingling Yuan, Tao Li
2014	—	`conf`	Leveraging distributed UPS energy for managing solar energy powered data centers. IGCC Longjun Liu, Hongbin Sun, Yang Hu, Jingmin Xin, Nanning Zheng, Tao Li
2014	J	`jnl`	Towards Automated Provisioning and Emergency Handling in Renewable Energy Powered Datacenters. J. Comput. Sci. Technol. Chao Li, Rui Wang, Yang Hu, Ruijin Zhou, Ming Liu, Longjun Liu, Jingling Yuan, Tao Li, Depei Qian
2013	A*	`conf`	Enabling datacenter servers to scale out economically and sustainably. MICRO Chao Li, Yang Hu, Ruijin Zhou, Ming Liu, Longjun Liu, Jingling Yuan, Tao Li
2012	J	`jnl`	Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC. IEICE Trans. Electron. Shouyi Yin, Yang Hu, Zhen Zhang, Leibo Liu, Shaojun Wei
2010	—	`conf`	Mixed-level modeling for network on chip infrastructure in SoC design. APCCAS Yang Hu, Shouyi Yin, Leibo Liu, Shaojun Wei