Yanbin Jiang

17 papers A 1B 3C 1Journal 8Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
Planner-R1: Reward Shaping Enables Efficient Agentic RL with Smaller LLMs.
CoRR
Siyu Zhu, Yanbin Jiang, Hejian Sang, Shao Tang, Qingquan Song, Biao He, Rohit Jain, Zhipeng Wang, Alborz Geramifard
2024 J jnl
Incorporating metapath interaction on heterogeneous information network for social recommendation.
Frontiers Comput. Sci.
Yanbin Jiang, Huifang Ma, Xiaohui Zhang, Zhixin Li, Liang Chang
2022 B conf
An Effective Two-way Metapath Encoder over Heterogeneous Information Network for Recommendation.
ICMR
Yanbin Jiang, Huifang Ma, Xiaohui Zhang, Zhixin Li, Liang Chang
2022 J jnl
Modelling risk and return awareness for p2p lending recommendation with graph convolutional networks.
Appl. Intell.
Yuhang Liu, Huifang Ma, Yanbin Jiang, Zhixin Li
2022 J jnl
Searching Target Communities with Outliers in attributed graph.
Knowl. Based Syst.
Qingqing Li, Huifang Ma, Ju Li, Zhixin Li, Yanbin Jiang
2021 B conf
Attentional Social Recommendation System with Graph Convolutional Network.
IJCNN
Yanbin Jiang, Huifang Ma, Yuhang Liu, Zhixin Li
2021 J jnl
Enhancing social recommendation via two-level graph attentional networks.
Neurocomputing
Yanbin Jiang, Huifang Ma, Yuhang Liu, Zhixin Li, Liang Chang
2021 J jnl
Learning to recommend via random walk with profile of loan and lender in P2P lending.
Expert Syst. Appl.
Yuhang Liu, Huifang Ma, Yanbin Jiang, Zhixin Li
2020 — conf
Exploring User Trust and Reliability for Recommendation: A Hypergraph Ranking Approach.
ICONIP (2)
Yanbin Jiang, Huifang Ma, Yuhang Liu, Zhixin Li
2020 — conf
Top-N Recommendation in P2P Lending: A Hybrid Graph Ranking Using Investor Profile.
ICONIP (2)
Yuhang Liu, Huifang Ma, Yanbin Jiang, Zhixin Li
2016 B conf
An artificial bee colony with self-adaptive operators and alterable search depth approach for intercell scheduling.
CEC
Yanbin Jiang, Pengyu Zhou, Rongxin Zhan, Xiang Li, Dongni Li
2001 J jnl
Technology mapping for high-performance static CMOS and pass transistor logic designs.
IEEE Trans. Very Large Scale Integr. Syst.
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
1999 A conf
An integrated algorithm for combined placement and libraryless technology mapping.
ICCAD
Yanbin Jiang, Sachin S. Sapatnekar
1998 C conf
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic.
ICCD
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
1998 — conf
Combined transistor sizing with buffer insertion for timing optimization.
CICC
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
1998 J jnl
Interleaving buffer insertion and transistor sizing into a single optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
1997 — conf
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs.
ISPD
Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar