Yan Lin - RankMe

23 papers A* 4A 9B 1Journal 8Unranked 1

Year	Rank	Type	Title / Venue / Authors
2012	J	`jnl`	Statistical Timing and Power Optimization of Architecture and Device for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He
2008	J	`jnl`	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. Yu Hu, Yan Lin, Lei He, Tim Tuan
2008	J	`jnl`	Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Yan Lin, Lei He, Mike Hutton
2008	A	`conf`	Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA Lerong Cheng, Yan Lin, Lei He
2007	J	`jnl`	Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He
2007	A	`conf`	Device and architecture concurrent optimization for FPGA transient soft error rate. ICCAD Yan Lin, Lei He
2007	J	`jnl`	Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Li, Yan Lin, Lei He
2007	A	`conf`	Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. DATE Yan Lin, Lei He
2007	J	`jnl`	Statistical placement for FPGAs considering. IET Comput. Digit. Tech. Yan Lin, Mike Hutton, Lei He
2007	A	`conf`	Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. FPGA Yan Lin, Lei He
2006	A	`conf`	An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED Yan Lin, Yu Hu, Lei He, Vijay Raghunat
2006	J	`jnl`	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yan Lin, Lei He
2006	B	`conf`	Placement and Timing for FPGAs Considering Variations. FPL Mike Hutton, Yan Lin, Lei He
2006	A*	`conf`	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC Yu Hu, Yan Lin, Lei He, Tim Tuan
2005	J	`jnl`	Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. Yan Lin, Fei Li, Lei He
2005	A*	`conf`	Device and architecture co-optimization for FPGA power reduction. DAC Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
2005	A	`conf`	FPGA device and architecture evaluation considering process variations. ICCAD Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
2005	A*	`conf`	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. DAC Yan Lin, Lei He
2005	A	`conf`	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA Yan Lin, Fei Li, Lei He
2005	—	`conf`	Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC Yan Lin, Fei Li, Lei He
2004	A*	`conf`	FPGA power reduction using configurable dual-Vdd. DAC Fei Li, Yan Lin, Lei He
2004	A	`conf`	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA Fei Li, Yan Lin, Lei He, Jason Cong
2004	A	`conf`	Vdd programmability to reduce FPGA interconnect power. ICCAD Fei Li, Yan Lin, Lei He