Yan Li

11 papers A* 1A 1Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
Toward Exploring Fault-Tolerant Neural Architectures: A Hierarchical Codesign Optimization Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao Chen, Liang Wang, Yan Li, Xiaoyang Zeng
2026 J jnl
When High Reliability Meets Low Cost: Exploring Approximate-TMR via Efficient Multiobjective Optimization Frameworks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yueming Hu, Yan Li, Xiaoyang Zeng
2024 J jnl
Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology.
Microelectron. J.
Chenyu Zhang, Yan Li, Wenfa Zhan, Wenping Geng, Ting Liang, Xiaoyang Zeng
2024 J jnl
Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors.
Microelectron. J.
Huaizhi Luo, Yongliang Li, Fei Zhao, Jiayi Zhang, Yan Li
2023 J jnl
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
2023 J jnl
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng
2022 — conf
An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits.
APCCAS
Shaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng
2021 J jnl
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
2021 A conf
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications.
DATE
Yan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori
2020 J jnl
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs
Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng
2020 A* conf
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
DAC
Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng