Yale N. Patt - RankMe

218 papers A* 104A 11B 7C 4Misc 4Journal 55Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	Enabling Ahead Prediction with Practical Energy Constraints. ISCA Lingzhe Chester Cai, Aniket Deshmukh, Yale N. Patt
2024	A*	`conf`	Alternate Path Fetch. ISCA Aniket Deshmukh, Lingzhe Chester Cai, Yale N. Patt
2024	—	`conf`	HCW 2024 Keynote: Hetero: Where we've been, Where we are, and What Next? IPDPS (Workshops) Yale N. Patt
2024	—	`conf`	Hetero: Where we've been, Where we are, and What Next? IPDPS (Workshops) Yale N. Patt
2024	J	`jnl`	The CORRECT First Course in Computing for Serious Students. Computer Yale N. Patt
2024	A*	`conf`	Timely, Efficient, and Accurate Branch Precomputation. MICRO Aniket Deshmukh, Lingzhe Chester Cai, Yale N. Patt
2022	A*	`conf`	SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection. HPCA Ali Fakhrzadehgan, Yale N. Patt, Prashant J. Nair, Moinuddin K. Qureshi
2021	A*	`conf`	Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches. MICRO Stephen Pruett, Yale N. Patt
2021	A*	`conf`	Criticality Driven Fetch. MICRO Aniket Deshmukh, Yale N. Patt
2020	A*	`conf`	BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches. MICRO Siavash Zangeneh, Stephen Pruett, Sangkug Lym, Yale N. Patt
2020	J	`jnl`	Dynamic Merge Point Prediction. CoRR Stephen Pruett, Yale N. Patt
2020	A*	`conf`	Tailored Page Sizes. ISCA Faruk Guvenilir, Yale N. Patt
2018	A*	`conf`	Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. MICRO Ben Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, Yale N. Patt
2017	—	`ed.`	2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017 SAMOS Yale N. Patt, S. K. Nandy
2016	A*	`conf`	Accelerating Dependent Cache Misses with an Enhanced Memory Controller. ISCA Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
2016	J	`jnl`	Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
2016	A*	`conf`	Continuous runahead: Transparent hardware acceleration for memory intensive workloads. MICRO Milad Hashemi, Onur Mutlu, Yale N. Patt
2016	J	`jnl`	Efficient Execution of Bursty Applications. IEEE Comput. Archit. Lett. Milad Hashemi, Debbie Marr, Doug Carmean, Yale N. Patt
2016	B	`conf`	Greater Performance and Better Efficiency: Predicated Execution has shown us the way. PACT Yale N. Patt
2015	A*	`conf`	Filtered runahead execution with a runahead buffer. MICRO Milad Hashemi, Yale N. Patt
2014	—	`conf`	Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache. ICS 25th Anniversary Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
2013	C	`conf`	Keynote 1 - VLSI 2.0: R&D Post Moore. VLSI-SoC Sani R. Nassif, Yale N. Patt, Magdy S. Abadir
2013	A*	`conf`	Utility-based acceleration of multithreaded applications on asymmetric CMPs. ISCA José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt
2012	A*	`conf`	Bottleneck identification and scheduling in multithreaded applications. ASPLOS José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt
2012	C	`conf`	Energy Savings via Dead Sub-Block Prediction. SBAC-PAD Marco A. Z. Alves, Khubaib, Eiman Ebrahimi, Veynu Narasiman, Carlos Villavieja, Philippe Olivier Alexandre Navaux, Yale N. Patt
2012	J	`jnl`	Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems. ACM Trans. Comput. Syst. Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt
2012	A	`conf`	High performance supercomputers: should the individual processor be more than a brick? ICS Yale N. Patt
2012	A*	`conf`	MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP. MICRO Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt
2012	A*	`conf`	Predicting Performance Impact of DVFS for Realistic Memory Systems. MICRO Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt
2011	J	`jnl`	Data Marshaling for Multicore Systems. IEEE Micro M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt
2011	—	`ch.`	HPS Microarchitecture. Encyclopedia of Parallel Computing Yale N. Patt
2011	A*	`conf`	Improving GPU performance via large warps and two-level warp scheduling. MICRO Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt
2011	A*	`conf`	Parallel application memory scheduling. MICRO Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt
2011	J	`jnl`	Prefetch-Aware Memory Controllers. IEEE Trans. Computers Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt
2011	A*	`conf`	Prefetch-aware shared resource management for multi-core systems. ISCA Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt
2011	J	`jnl`	Top Picks [Guest editors' introduction]. IEEE Micro Yale N. Patt, Onur Mutlu
2010	J	`jnl`	Accelerating Critical Section Execution with Asymmetric Multicore Architectures. IEEE Micro M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt
2010	A*	`conf`	Data marshaling for multi-core architectures. ISCA M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt
2010	A*	`conf`	Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. ASPLOS Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt
2010	B	`conf`	Feedback-directed pipeline parallelism. PACT M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, Yale N. Patt
2010	—	`ed.`	High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings HiPEAC Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell
2009	A*	`conf`	Accelerating critical section execution with asymmetric multi-core architectures. ASPLOS M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt
2009	A*	`conf`	Coordinated control of multiple prefetchers in multi-core systems. MICRO Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt
2009	A*	`conf`	Flexible reference-counting-based hardware acceleration for garbage collection. ISCA José A. Joao, Onur Mutlu, Yale N. Patt
2009	A*	`conf`	Improving memory bank-level parallelism in the presence of prefetching. MICRO Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt
2009	A*	`conf`	Multi-core demands multi-interfaces. HPCA Yale N. Patt
2009	B	`conf`	Multi-core demands multi-interfaces. PPoPP Yale N. Patt
2009	A*	`conf`	Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. HPCA Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
2009	—	`conf`	The Challenges of Multicore: Information and Mis-Information. ARCS Yale N. Patt
2009	J	`jnl`	Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. IEEE Trans. Computers Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
2009	—	`conf`	What Else Is Broken? Can We Fix It? SAMOS Yale N. Patt
2008	A*	`conf`	Achieving Out-of-Order Performance with Almost In-Order Complexity. ISCA Francis Tseng, Yale N. Patt
2008	—	`conf`	Can They Be Fixed: Some Thoughts After 40 Years in the Business. SAMOS Yale N. Patt
2008	J	`jnl`	Dynamic Predication of Indirect Jumps. IEEE Comput. Archit. Lett. José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt
2008	A*	`conf`	Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. ASPLOS M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt
2008	A*	`conf`	Improving the performance of object-oriented languages with dynamic predication of indirect jumps. ASPLOS José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt
2008	A*	`conf`	Performance-aware speculation control using wrong path usefulness prediction. HPCA Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt
2008	A*	`conf`	Prefetch-Aware DRAM Controllers. MICRO Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt
2008	J	`jnl`	Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
2007	A*	`conf`	Adaptive insertion policies for high performance caching. ISCA Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
2007	J	`jnl`	Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. IEEE Micro Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
2007	J	`jnl`	Dynamic Predication of Indirect Jumps. IEEE Comput. Archit. Lett. José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt
2007	A*	`conf`	Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. HPCA Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt
2007	A*	`conf`	Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. HPCA Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt
2007	A	`conf`	Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. CGO Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
2007	J	`jnl`	Single-Threaded vs. Multithreaded: Where Should We Focus? IEEE Micro Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag
2007	Misc	`conf`	The Transformation Hierarchy in the Era of Multi-core. HiPC Yale N. Patt
2007	A*	`conf`	VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
2006	A	`conf`	2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. CGO Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt
2006	A*	`conf`	A Case for MLP-Aware Cache Replacement. ISCA Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt
2006	J	`jnl`	Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. IEEE Trans. Computers Onur Mutlu, Hyesoon Kim, Yale N. Patt
2006	A*	`conf`	Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? ISCA Yale N. Patt
2006	A*	`conf`	Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. MICRO Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
2006	J	`jnl`	Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. IEEE Micro Onur Mutlu, Hyesoon Kim, Yale N. Patt
2006	J	`jnl`	Foreword. IEEE Comput. Archit. Lett. Jean-Luc Gaudiot, Yale N. Patt, Kevin Skadron
2006	A*	`conf`	Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. MICRO Moinuddin K. Qureshi, Yale N. Patt
2006	J	`jnl`	Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. IEEE Micro Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark
2005	A	`conf`	A Unifying Theory of Distributed Processing (Or, The Chutzpah One Should Expect When You Invite a Microarchitect into Your Sandbox). IPDPS Yale N. Patt
2005	A*	`conf`	Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO Onur Mutlu, Hyesoon Kim, Yale N. Patt
2005	J	`jnl`	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. IEEE Trans. Computers Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
2005	A	`conf`	Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. DSN Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt
2005	J	`jnl`	On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. IEEE Comput. Archit. Lett. Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
2005	A*	`conf`	Techniques for Efficient Processing in Runahead Execution Engines. ISCA Onur Mutlu, Hyesoon Kim, Yale N. Patt
2005	A*	`conf`	The V-Way Cache: Demand Based Associativity via Global Replacement. ISCA Moinuddin K. Qureshi, David Thompson, Yale N. Patt
2005	C	`conf`	The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints? AICCSA Yale N. Patt
2005	J	`jnl`	Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. Int. J. Parallel Program. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
2005	A*	`conf`	Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. MICRO Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
2004	C	`conf`	Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. SBAC-PAD Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
2004	—	`book`	Introduction to computing systems - from bits and gates to C and beyond (2. ed.). Yale N. Patt, Sanjay J. Patel
2004	B	`conf`	Opening and keynote 1. ISPASS Yale N. Patt
2004	B	`conf`	The future of simulation: A field of dreams. ISPASS Brad Calder, Daniel Citron, Yale N. Patt, James E. Smith
2004	—	`conf`	Understanding the effects of wrong-path memory references on processor performance. WMPI Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
2004	A*	`conf`	Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. MICRO David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt
2003	A	`conf`	Partitioned first-level cache design for clustered microarchitectures. ICS Paul Racunas, Yale N. Patt
2003	A*	`conf`	Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. HPCA Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
2003	J	`jnl`	Runahead Execution: An Effective Alternative to Large Instruction Windows. IEEE Micro Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
2003	Misc	`conf`	Teaching and teaching computer architecture: two very different topics: (some opinions about each). WCAE Yale N. Patt
2003	Misc	`conf`	The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like? HiPC Yale N. Patt
2002	A*	`ed.`	29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA ISCA Yale N. Patt, Dirk Grunwald, Kevin Skadron
2002	A*	`conf`	Difficult-Path Branch Prediction Using Subordinate Microthreads. ISCA Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz
2002	Misc	`conf`	Handling of packet dependencies: a critical issue for highly parallel network processors. CASES Stephen W. Melvin, Yale N. Patt
2002	A*	`conf`	Microarchitectural support for precomputation microthreads. MICRO Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt
2002	A*	`conf`	Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. HPCA Mary D. Brown, Yale N. Patt
2001	A*	`ed.`	Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001 MICRO Yale N. Patt, Josh Fisher, Paolo Faraboschi, Kevin Skadron
2001	A	`conf`	Programming early considered harmful. SIGCSE Judith L. Gersting, Peter B. Henderson, Philip Machanick, Yale N. Patt
2001	J	`jnl`	Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proc. IEEE Yale N. Patt
2001	A*	`conf`	Select-free instruction scheduling logic. MICRO Mary D. Brown, Jared Stark, Yale N. Patt
2000	—	`conf`	Higher and Higher Performance Microprocessors: Are The Problems Just Too Hard To Solve? EUROMICRO Yale N. Patt
2000	A*	`conf`	On pipelining dynamic instruction scheduling logic. MICRO Jared Stark, Mary D. Brown, Yale N. Patt
2000	J	`jnl`	Soft updates: a solution to the metadata update problem in file systems. ACM Trans. Comput. Syst. Gregory R. Ganger, Marshall K. McKusick, Craig A. N. Soules, Yale N. Patt
1999	—	`conf`	Computer architecture education: mechanical engineers need it too. WCAE@HPCA Yale N. Patt
1999	J	`jnl`	Evaluation of Design Options for the Trace Cache Fetch Mechanism. IEEE Trans. Computers Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt
1999	A*	`conf`	Simultaneous Subordinate Microthreading (SSMT). ISCA Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt, Yale N. Patt
1998	—	`conf`	Alternative Implementations of Two-Level Adaptive Branch Prediction. 25 Years ISCA: Retrospectives and Reprints Tse-Yu Yeh, Yale N. Patt
1998	A*	`conf`	An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
1998	—	`conf`	HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. 25 Years ISCA: Retrospectives and Reprints Wen-mei W. Hwu, Yale N. Patt
1998	A*	`conf`	Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA Sanjay J. Patel, Marius Evers, Yale N. Patt
1998	J	`jnl`	Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. Int. J. Parallel Program. Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
1998	A*	`conf`	Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. MICRO Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
1998	—	`conf`	Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. 25 Years ISCA: Retrospectives and Reprints Tse-Yu Yeh, Yale N. Patt
1998	—	`conf`	Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. 25 Years ISCA: Retrospectives and Reprints Wen-mei W. Hwu, Yale N. Patt
1998	J	`jnl`	Using System-Level Models to Evaluate I/O Subsystem Designs. IEEE Trans. Computers Gregory R. Ganger, Yale N. Patt
1998	A*	`conf`	Variable Length Path Branch Prediction. ASPLOS Jared Stark, Marius Evers, Yale N. Patt
1997	A*	`conf`	Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. MICRO Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
1997	J	`jnl`	Identifiying Obstacles in the Path to More. Computer Yale N. Patt
1997	J	`jnl`	Improving branch prediction accuracy by reducing pattern history table interference. Int. J. Parallel Program. Po-Yung Chang, Marius Evers, Yale N. Patt
1997	J	`jnl`	One Billion Transistors, One Uniprocessor, One Chip. Computer Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark
1997	J	`jnl`	Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution. Int. J. Parallel Program. Stéphan Jourdan, Jared Stark, Tse-Hao Hsing, Yale N. Patt
1997	A*	`conf`	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. MICRO Jared Stark, Paul Racunas, Yale N. Patt
1997	A*	`conf`	Target Prediction for Indirect Jumps. ISCA Po-Yung Chang, Eric Hao, Yale N. Patt
1997	A*	`conf`	The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. ISCA Eric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt
1997	—	`conf`	Using Non-Volatile Storage to Improve the Reliability of RAID5 Disk Arrays. FTCS Robert Y. Hou, Yale N. Patt
1996	J	`jnl`	Branch Classification: New Mechanism for Improving Branch Predictor Performance. Int. J. Parallel Program. Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
1996	—	`conf`	Education in computer science and computer engineering starts with computer architecture. WCAE@HPCA Yale N. Patt
1996	J	`jnl`	First Courses and Fundamentals. ACM Comput. Surv. Yale N. Patt
1996	—	`conf`	Improving branch prediction accuracy by reducing pattern history table interference. IEEE PACT Po-Yung Chang, Marius Evers, Yale N. Patt
1996	A*	`conf`	Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. MICRO Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
1996	J	`jnl`	Microarchitecture, Compilers and Algorithms. ACM Comput. Surv. Yale N. Patt
1996	—	`conf`	The effects of mispredicted-path execution on branch prediction structures. IEEE PACT Stéphan Jourdan, Tse-Hao Hsing, Jared Stark, Yale N. Patt
1996	A*	`conf`	Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. ISCA Marius Evers, Po-Yung Chang, Yale N. Patt
1996	J	`jnl`	Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution. Int. J. Parallel Program. Po-Yung Chang, Eric Hao, Yale N. Patt, Pohua P. Chang
1995	A*	`conf`	Alternative implementations of hybrid branch predictors. MICRO Po-Yung Chang, Eric Hao, Yale N. Patt
1995	—	`conf`	Components of a computer architecture education. WCAE@HPCA Yale N. Patt
1995	—	`conf`	Components of a computer architecture education: optimal and suboptimal. WCAE@ISCA Yale N. Patt
1995	J	`jnl`	Enhancing instruction scheduling with a block-structured ISA. Int. J. Parallel Program. Stephen W. Melvin, Yale N. Patt
1995	A*	`conf`	On-Line Extraction of SCSI Disk Drive Parameters. SIGMETRICS Bruce L. Worthington, Gregory R. Ganger, Yale N. Patt, John Wilkes
1995	J	`jnl`	Scanning the Issue - Special Issue on Microprocessors. Proc. IEEE Yale N. Patt
1995	—	`conf`	Track Piggybacking: An Improved Rebuild Algorithm for RAID5 Disk Arrays. ICPP (1) Robert Y. Hou, Yale N. Patt
1995	B	`conf`	Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution. PACT Po-Yung Chang, Eric Hao, Yale N. Patt, Pohua P. Chang
1994	A*	`conf`	Branch classification: a new mechanism for improving branch predictor performance. MICRO Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
1994	J	`jnl`	Disk Arrays: High-Performance, High-Reliability Storage Subsystems. Computer Gregory R. Ganger, Bruce L. Worthington, Robert Y. Hou, Yale N. Patt
1994	A*	`conf`	Facilitating superscalar processing via a combined static/dynamic register renaming scheme. MICRO Eric Sprangle, Yale N. Patt
1994	A*	`conf`	Metadata Update Performance in File Systems. OSDI Gregory R. Ganger, Yale N. Patt
1994	A*	`conf`	Scheduling Algorithms for Modern Disk Drives. SIGMETRICS Bruce L. Worthington, Gregory R. Ganger, Yale N. Patt
1994	J	`jnl`	The I/O Subsystem - A Candidate for Improvement: Guest Editor's Introduction. Computer Yale N. Patt
1994	A*	`conf`	The effect of speculatively updating branch history on branch prediction accuracy, revisited. MICRO Eric Hao, Po-Yung Chang, Yale N. Patt
1993	A*	`conf`	A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. ISCA Tse-Yu Yeh, Yale N. Patt
1993	A*	`conf`	A comparative performance evaluation of various state maintenance mechanisms. MICRO Michael Butler, Yale N. Patt
1993	A*	`conf`	Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. MICRO Tse-Yu Yeh, Yale N. Patt
1993	—	`conf`	Comparing Rebuild Algorithms for Mirrored and RAID5 Disk Arrays. SIGMOD Conference Robert Y. Hou, Yale N. Patt
1993	A	`conf`	Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. International Conference on Supercomputing Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
1993	A*	`conf`	The Process-Flow Model: Examining I/O Performance from the System's Point of View. SIGMETRICS Gregory R. Ganger, Yale N. Patt
1993	A	`conf`	Trading Disk Capacity for Performance. HPDC Robert Y. Hou, Yale N. Patt
1992	A*	`conf`	A comprehensive instruction fetch mechanism for a processor supporting speculative execution. MICRO Tse-Yu Yeh, Yale N. Patt
1992	A*	`conf`	Alternative Implementations of Two-Level Adaptive Branch Prediction. ISCA Tse-Yu Yeh, Yale N. Patt
1992	J	`jnl`	An experimental single-chip data flow CPU. IEEE J. Solid State Circuits Gregory A. Uvieghara, Wen-mei W. Hwu, Yoshinobu Nakagome, Deog-Kyoon Jeong, David D. Lee, David A. Hodges, Yale N. Patt
1992	A*	`conf`	An investigation of the performance of various dynamic scheduling techniques. MICRO Michael Butler, Yale N. Patt
1992	J	`jnl`	Highest performance computing machines. Microprocess. Microprogramming Yale N. Patt
1992	J	`jnl`	Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing. J. Parallel Distributed Comput. Howard Jay Siegel, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug DeGroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jamp, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, Benjamin W. Wah
1991	J	`jnl`	Experimental Research in Computer Architecture - Guest Editor's Introduction to the Special Issue. Computer Yale N. Patt
1991	A*	`conf`	Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques. ISCA Stephen W. Melvin, Yale N. Patt
1991	A*	`conf`	Single Instruction Stream Parallelism is Greater Than Two. ISCA Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
1991	A*	`conf`	The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. MICRO Michael Butler, Yale N. Patt
1991	A*	`conf`	Two-Level Adaptive Training Branch Prediction. MICRO Tse-Yu Yeh, Yale N. Patt
1990	—	`conf`	An Area-Efficient Register Alias Table for Implementing HPS. ICPP (1) Michael Butler, Yale N. Patt
1989	A*	`conf`	A High Performance Prolog Processor with Multiple Function Units. ISCA Ashok Singhal, Yale N. Patt
1989	J	`jnl`	Alternative implementations of Prolog: the microarchitecture perspective. IEEE Trans. Syst. Man Cybern. Yale N. Patt
1989	A*	`conf`	Microarchitecture choices (implementation of the VAX). MICRO Yale N. Patt
1989	A	`conf`	Performance benefits of large execution atomic units in dynamically scheduled machines. ICS Stephen W. Melvin, Yale N. Patt
1989	J	`jnl`	Real Machines: Design Choices / Engineering Trade-Offs - Guest Editor's Introduction. Computer Yale N. Patt
1989	—	`conf`	Unification Parallelism: How Much Can We Exploit? NACLP Ashok Singhal, Yale N. Patt
1988	A*	`conf`	Hardware support for large atomic units in dynamically scheduled machines. MICRO Stephen W. Melvin, Michael Shebanow, Yale N. Patt
1988	A	`conf`	Hierarchical registers for scientific computers. ICS John A. Swensen, Yale N. Patt
1988	A*	`conf`	Implementing a Prolog machine with multiple functional units. MICRO Ashok Singhal, Yale N. Patt
1988	A*	`ed.`	Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988 MICRO Yale N. Patt
1988	A*	`conf`	The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels. SIGMETRICS Stephen W. Melvin, Yale N. Patt
1987	B	`conf`	Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer. ICLP Jeffrey D. Gee, Stephen W. Melvin, Yale N. Patt
1987	J	`jnl`	Aquarius. SIGARCH Comput. Archit. News Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy
1987	J	`jnl`	Checkpoint Repair for High-Performance Out-of-Order Execution Machines. IEEE Trans. Computers Wen-mei W. Hwu, Yale N. Patt
1987	A*	`conf`	Checkpoint Repair for Out-of-order Execution Machines. ISCA Wen-mei W. Hwu, Yale N. Patt
1987	A*	`conf`	Exploiting horizontal and vertical concurrency via the HPSm microprocessor. MICRO Wen-mei W. Hwu, Yale N. Patt
1987	A*	`conf`	Fast Temporary Storage for Serial and Parallel Execution. ISCA John A. Swensen, Yale N. Patt
1987	A*	`conf`	On tuning the microarchitecture of an HPS implementation of the VAX. MICRO James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt
1987	A*	`conf`	SPAM: a microcode based tool for tracing operating system events. MICRO Stephen W. Melvin, Yale N. Patt
1986	A*	`conf`	A microcode-based environment for noninvasive performance analysis. MICRO Stephen W. Melvin, Yale N. Patt
1986	—	`conf`	Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. COMPCON Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei
1986	A*	`conf`	HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. ISCA Wen-mei W. Hwu, Yale N. Patt
1986	—	`conf`	High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation. COMPCON Alvin M. Despain, Yale N. Patt, Tep P. Dobry, Jung-Herng Chang, Wayne Citrin
1986	A*	`conf`	Run-time generation of HPS microinstructions from a VAX instruction stream. MICRO Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen
1986	A*	`conf`	The implementation of Prolog via VAX 8600 microcode. MICRO Jeffrey D. Gee, Stephen W. Melvin, Yale N. Patt
1985	—	`conf`	Aquarius - A High Performance Computing System for Symbolic/Numeric Applications. COMPCON Alvin M. Despain, Yale N. Patt
1985	A*	`conf`	Compiling Prolog into microcode: a case study using the NCR/32-000. MICRO Barry S. Fagin, Yale N. Patt, Vason P. Srini, Alvin M. Despain
1985	A*	`conf`	Critical issues regarding HPS, a high performance microarchitecture. MICRO Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow
1985	A*	`conf`	HPS, a new microarchitecture: rationale and introduction. MICRO Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow
1985	A*	`conf`	Microcode and the protection of intellectual effort. MICRO Yale N. Patt, John K. Ahlstrom
1985	A*	`conf`	Performance Studies of a Prolog Machine Architecture. ISCA Tep P. Dobry, Alvin M. Despain, Yale N. Patt
1985	J	`jnl`	Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic - Implementation Issues, Measurements, and Analysis. IEEE Trans. Computers David B. Aspinwall, Yale N. Patt
1984	A*	`conf`	Alternative proposals for implementing Prolog concurrently and implications regarding their respective microarchitectures. MICRO Carl Ponder, Yale N. Patt
1984	A*	`conf`	Design decisions influencing the microarchitecture for a Prolog machine. MICRO Tep P. Dobry, Yale N. Patt, Alvin M. Despain
1984	—	`conf`	The Aquarius Project. COMPCON Alvin M. Despain, Yale N. Patt
1979	—	`conf`	Some results on the asymptotic behavior of functions on subsets of the natural numbers. ACM Southeast Regional Conference David F. McAllister, Yale N. Patt
1977	J	`jnl`	Independent necessary conditions for functional completeness in m-valued logic. Notre Dame J. Formal Log. Yale N. Patt
1975	J	`jnl`	Some Clarifications of the Concept of a Garden-of-Eden Configuration. J. Comput. Syst. Sci. Serafino Amoroso, Gerald Cooper, Yale N. Patt
1973	J	`jnl`	Optimal and Near-Optimal Universal Logic Modules with Interconnected External Terminals. IEEE Trans. Computers Yale N. Patt
1972	J	`jnl`	Decision Procedures for Surjectivity and Injectivity of Parallel Maps for Tessellation Structures. J. Comput. Syst. Sci. Serafino Amoroso, Yale N. Patt
1972	J	`jnl`	Minimum Search Tree Structures for Data Partitioned into Pages. IEEE Trans. Computers Yale N. Patt
1969	J	`jnl`	Variable length tree structures having minimum average search time. Commun. ACM Yale N. Patt
1967	—	`conf`	A complex logic module for the synthesis of combinational switching circuits. AFIPS Spring Joint Computing Conference Yale N. Patt