Yajun Ha

172 papers A* 6A 5B 14C 19Misc 5Journal 78Unranked 44
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Complementary 3T-Based eDRAM Macro for High-Density Dual-Direction CAM and Logic-in-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Lintao Lan, Yuxin Zhou, Jincheng Wang, Yifei Li, Bin Ning, Yuhao Shu, Hui Wang, Yajun Ha
2026 J jnl
ACIMC: A 342.7-TOPS/mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuhao Shu, Hongtu Zhang, Yifei Li, Jincheng Wang, Hao Sun, Weiqiang Liu, Yajun Ha
2026 J jnl
ESACO: Fast E-Graph Extraction via Orchestrated Simulated Annealing-Based Local Search and Ant Colony Optimization-Based Global Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Li, Lin Li, Heng Yu, Yajun Ha
2026 J jnl
FPGA Routing Congestion Prediction via Graph Learning-Aided Conditional GAN.
ACM Trans. Design Autom. Electr. Syst.
Qingyu Yang, Jingjin Li, Rui Li, Yuting He, Yajun Ha, Linlin Shen, Ruibin Bai, Heng Yu
2026 J jnl
VOS-NN: An Efficient Bitonic-Based Voxel-Enhanced Octree Nearest Neighbor Search Accelerator for Large-Scale Point Cloud.
IEEE Trans. Circuits Syst. II Express Briefs
Hao Sun, Yaotang Wu, Yongming Tang, Yajun Ha
2025 J jnl
A 5T0C eDRAM-Based Content Addressable Memory for High-Density Searching and Logic-in-Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Jincheng Wang, Yuhao Shu, Lintao Lan, Yifei Li, Bin Ning, Yuxin Zhou, Hongtu Zhang, Yajun Ha
2025 J jnl
A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junge Xu, Fan Zhang, Wenguang Jin, Kun Yang, Zeke Wang, Weixiong Jiang, Yajun Ha
2025 J jnl
An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search.
ACM Trans. Reconfigurable Technol. Syst.
Qi Deng, Hao Sun, Yuhao Shu, Jianzhong Xiao, Weixiong Jiang, Hui Wang, Yajun Ha
2025 J jnl
An FPGA-Based Real-Time Loop Closure Detection Framework With Ultra-Fast Descriptor Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shijie Meng, Qi Deng, Weixiong Jiang, Jinjie Huang, Hao Sun, Yajun Ha
2025 J jnl
Fast FPGA Accelerator of Graph Cut Algorithm With Threshold Global Relabel and Inertial Push.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guangyao Yan, Xinzhe Liu, Hui Wang, Yajun Ha
2025 J jnl
FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in Embedded Systems.
IEEE Trans. Computers
Jingjin Li, Weixiong Jiang, Yuting He, Qingyu Yang, Anqi Gao, Yajun Ha, Ender Özcan, Ruibin Bai, Tianxiang Cui, Heng Yu
2025 J jnl
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shen Zhang, Bin Ning, Guangyao Yan, Xinzhe Liu, Weixiong Jiang, Yajun Ha
2025 C conf
ROFD: Event-based 5k-fps Real-Time Optical Flow Detector for Transient Radiant Expanding Flares.
ISCAS
Shen Zhang, Boyi Wei, Jing Jin, Yibo Zhang, Wenzhe Zheng, Yan Shen, Weixiong Jiang, Chenyang Shi, Yajun Ha
2025 J jnl
RSQC: Recursive Sparse QUBO Construction for Quantum Annealing Machines.
IEEE Trans. Computers
Jianwen Luo, Yuhao Shu, Yajun Ha
2025 J jnl
RefSCAT-2.0: Formal Verification of Large-Scale Optimized Multipliers via Quantum-Inspired Ant Colony Optimization-Based Reference Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang, Yajun Ha
2025 J jnl
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang, Yajun Ha
2024 C conf
EarFDA: A Lightweight and Energy-Efficient Fall Detection Accelerator for Ear-Worn Devices.
ISCAS
Zhaodong Lv, Hao Sun, Yuhao Shu, Yajun Ha
2024 J jnl
Fast Constraints Tuning via Transfer Learning and Multiobjective Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng Zhang, Zheng Zhang, Yifan Niu, Jiayi Li, Zewei Chen, Guoqing Li, Yajun Ha, Tinghuan Chen
2024 C conf
Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway.
ISCAS
Yi Wang, Yuanjin Zheng, Yajun Ha
2024 J jnl
Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway.
CoRR
Yi Wang, Yuanjin Zheng, Yajun Ha
2024 J jnl
Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoxuan Peng, Xiaohu Ge, Yajun Ha
2024 C conf
The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory.
ISCAS
Yifei Li, Yuxin Zhou, Yuhao Shu, Hongyu Chen, Yajun Ha
2024 J jnl
eCIMC: A603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations.
IEEE J. Solid State Circuits
Yuhao Shu, Hongtu Zhang, Qi Deng, Hao Sun, Zhaodong Lv, Yifei Li, Yajun Ha
2023 — conf
A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path.
CICC
Yifei Li, Jian Chen, Yuqi Wang, Zihan Yin, Hongyu Chen, Yajun Ha
2023 J jnl
A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weixiong Jiang, Heng Yu, Yajun Ha
2023 J jnl
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lin Li, Rui Li, Yajun Ha
2023 J jnl
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V
IEEE Trans. Very Large Scale Integr. Syst.
Yuqi Wang, Shen Zhang, Yifei Li, Jian Chen, Wenfeng Zhao, Yajun Ha
2023 J jnl
AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weixiong Jiang, Heng Yu, Fupeng Chen, Yajun Ha
2023 J jnl
An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Sun, Qi Deng, Xinzhe Liu, Yuhao Shu, Yajun Ha
2023 — conf
An Energy-efficient and Fast KNN Search Accelerator for Large Scale Point Cloud Map.
ICECS
Yunhao Hu, Hao Sun, Chunxu Guo, Qi Deng, Yajun Ha
2023 — conf
CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing.
CICC
Yuhao Shu, Hongtu Zhang, Qi Deng, Hao Sun, Yajun Ha
2023 C conf
CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing.
ISCAS
Yuhao Shu, Hongtu Zhang, Hao Sun, Qi Deng, Yajun Ha
2023 J jnl
Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Li, Heng Yu, Lin Li, Yajun Ha
2023 J jnl
Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications.
CoRR
Yuhao Shu, Hongtu Zhang, Hao Sun, Mengru Zhang, Wenfeng Zhao, Qi Deng, Zhidong Tang, Yumeng Yuan, Yongqi Hu, Yu Gu, Xufeng Kou, Yajun Ha
2023 — conf
Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder.
ICECS
Xinzhe Liu, Jianwen Luo, David Blinder, Fupeng Chen, Heng Yu, Peter Schelkens, Francky Catthoor, Yajun Ha
2023 A* conf
Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture.
DAC
Guangyao Yan, Xinzhe Liu, Hui Wang, Yajun Ha
2023 J jnl
HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha
2023 — conf
NORB: A Stream-Based and Non-Blocking FPGA Accelerator for ORB Feature Extraction.
ICECS
Qixing Zhang, Hao Sun, Qi Deng, Heng Yu, Yajun Ha
2023 J jnl
Outgoing Editorial.
IEEE Trans. Circuits Syst. II Express Briefs
Yajun Ha
2023 C conf
RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles.
ISCAS
Jianzhong Xiao, Hao Sun, Qi Deng, Xinzhe Liu, Hongtu Zhang, Chengzhang He, Yuhao Shu, Yajun Ha
2023 J jnl
WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongtu Zhang, Yuhao Shu, Qi Deng, Hao Sun, Wenfeng Zhao, Yajun Ha
2022 J jnl
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations.
IEEE Trans. Very Large Scale Integr. Syst.
Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha
2022 C conf
An Ultra Energy Efficient Streaming-based FPGA Accelerator for Lightweight Neural Network.
ISCAS
Shaoyi Chen, Zhiqi Zhou, Yajun Ha
2022 J jnl
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA.
IEEE Trans. Very Large Scale Integr. Syst.
Weixiong Jiang, Heng Yu, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha
2022 J jnl
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhengpeng Liao, Deyang Jiang, Xiaochun Liu, Andreas Velten, Yajun Ha, Xin Lou
2022 — conf
Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs.
APCCAS
Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha
2022 J jnl
Incoming Editorial.
IEEE Trans. Circuits Syst. II Express Briefs
Yajun Ha
2022 J jnl
Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fupeng Chen, Heng Yu, Weixiong Jiang, Yajun Ha
2022 J jnl
Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guangyao Yan, Xinzhe Liu, Fupeng Chen, Hui Wang, Yajun Ha
2022 — conf
Unified Lightweight Authenticated Encryption for Resource-Constrained Electronic Control Unit.
ICECS 2022
Chunxu Guo, Yi Wang, Fupeng Chen, Yajun Ha
2022 A conf
WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization.
ICCAD
Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao
2021 J jnl
A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Hongtu Zhang, Yuhao Shu, Weixiong Jiang, Zihan Yin, Wenfeng Zhao, Yajun Ha
2021 C conf
A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness.
ISCAS
Yi Wang, Marc Stöttinger, Yajun Ha
2021 J jnl
An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles.
IEEE Trans. Circuits Syst. II Express Briefs
Qi Deng, Hao Sun, Fupeng Chen, Yuhao Shu, Hui Wang, Yajun Ha
2021 J jnl
Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access.
IEEE Trans. Circuits Syst. II Express Briefs
Jian Chen, Wenfeng Zhao, Yuqi Wang, Yajun Ha
2021 J jnl
Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jian Chen, Wenfeng Zhao, Yuqi Wang, Yajun Ha
2021 A* conf
Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation.
DAC
Xinzhe Liu, Fupeng Chen, Raees Kizhakkumkara Muhamad, David Blinder, Dessislava Nikolova, Peter Schelkens, Francky Catthoor, Yajun Ha
2021 C conf
CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation.
ISCAS
Fupeng Chen, Xinzhe Liu, Heng Yu, Yajun Ha
2021 J jnl
DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return.
IEEE Trans. Computers
Heng Yu, Yajun Ha, Bharadwaj Veeravalli, Fupeng Chen, Hesham El-Sayed
2021 J jnl
Guest Editorial Special Issue on the 2021 IEEE International Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Yajun Ha, Edoardo Bonizzoni
2021 J jnl
Guest Editorial Special Issue on the 2021 ISICAS: A CAS Journal Track Symposium.
IEEE Trans. Circuits Syst. II Express Briefs
Yajun Ha, Edoardo Bonizzoni
2021 J jnl
Hierarchical Topometric Representation of 3D Robotic Maps.
CoRR
Zhenpeng He, Hao Sun, Jiawei Hou, Yajun Ha, Sören Schwertfeger
2021 J jnl
Hierarchical topometric representation of 3D robotic maps.
Auton. Robots
Zhenpeng He, Hao Sun, Jiawei Hou, Yajun Ha, Sören Schwertfeger
2021 A* conf
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer.
DAC
Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha
2020 J jnl
A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions.
IEEE Trans. Circuits Syst. I Regul. Pap.
Huaqing Sun, Yuanyong Luo, Yajun Ha, Yinghuan Shi, Yang Gao, Qinghong Shen, Hongbing Pan
2020 C conf
An Accurate FPGA Online Delay Monitor Supporting All Timing Paths.
ISCAS
Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha
2020 A* conf
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs.
DAC
Rui Li, Heng Yu, Weixiong Jiang, Yajun Ha
2020 J jnl
Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles.
IEEE Trans. Circuits Syst. II Express Briefs
Hao Sun, Xinzhe Liu, Qi Deng, Weixiong Jiang, Shaobo Luo, Yajun Ha
2020 C conf
Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing.
ISCAS
Yuqi Wang, Jian Chen, Yu Pu, Yajun Ha
2020 J jnl
Guest Editorial Special Issue on the 2020 IEEE International Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Yajun Ha, Edoardo Bonizzoni
2020 J jnl
Guest Editorial Special Issue on the 2020 ISICAS: A CAS Journal Track Symposium.
IEEE Trans. Circuits Syst. II Express Briefs
Yajun Ha, Edoardo Bonizzoni
2020 — conf
Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects.
LASCAS
Ruiqi Luo, Xiaolei Chen, Yajun Ha
2020 J jnl
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions.
IEEE Trans. Very Large Scale Integr. Syst.
Hongxi Dong, Manzhen Wang, Yuanyong Luo, Muhan Zheng, Mengyu An, Yajun Ha, Hongbing Pan
2020 J jnl
Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles.
ACM Trans. Embed. Comput. Syst.
Fupeng Chen, Heng Yu, Yajun Ha
2020 — conf
Vulnerability of Deep Learning Model based Anomaly Detection in Vehicle Network.
MWSCAS
Yi Wang, Dan Wei Ming Chia, Yajun Ha
2019 — conf
Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree.
ISVLSI
Xinzhe Liu, Fupeng Chen, Yajun Ha
2019 — conf
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing.
ASICON
Jian Chen, Wenfeng Zhao, Yajun Ha
2019 — conf
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design.
SoCC
Wenfeng Zhao, Biao Sun, Jian Chen, Yajun Ha
2019 J jnl
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base".
IEEE Trans. Very Large Scale Integr. Syst.
Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan
2019 — conf
Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC.
SoCC
Weixiong Jiang, Heng Yu, Yajun Ha
2019 — conf
Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS.
ICECS
Weixiong Jiang, Heng Yu, Xinzhe Liu, Yajun Ha
2019 J jnl
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base.
IEEE Trans. Very Large Scale Integr. Syst.
Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan
2018 J jnl
A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration.
ACM Trans. Embed. Comput. Syst.
Tian Huang, Yongxin Zhu, Yajun Ha, Xu Wang, Meikang Qiu
2018 — conf
Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications.
ACA
Yun Liang, Shuo Wang, Tulika Mitra, Yajun Ha
2017 J jnl
A DFA-Resistant and Masked PRESENT with Area Optimization for RFID Applications.
ACM Trans. Embed. Comput. Syst.
Yi Wang, Yajun Ha
2017 J jnl
An FPGA-Based Cloud System for Massive ECG Data Analysis.
IEEE Trans. Circuits Syst. II Express Briefs
Xu Wang, Yongxin Zhu, Yajun Ha, Meikang Qiu, Tian Huang
2017 J jnl
An energy-efficient system on a programmable chip platform for cloud applications.
J. Syst. Archit.
Xu Wang, Yongxin Zhu, Yajun Ha, Meikang Qiu, Tian Huang, Xueming Si, Jiangxing Wu
2017 — conf
Analysis and design of energy-efficient data-dependent SRAM.
ASICON
Wenfeng Zhao, Ang Li, Yi Wang, Yajun Ha
2017 — conf
Quality Optimization of Resilient Applications under Temperature Constraints.
Conf. Computing Frontiers
Heng Yu, Yajun Ha, Jing Wang
2016 J jnl
An Optimized Logarithmic Converter With Equal Distribution of Relative Errors.
IEEE Trans. Circuits Syst. II Express Briefs
Mengyao Zhu, Yajun Ha, Chengcun Gu, Liuchuang Gao
2016 C conf
High throughput and resource efficient AES encryption/decryption for SANs.
ISCAS
Yi Wang, Yajun Ha
2016 B conf
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning.
FPL
Chin Hau Hoo, Yajun Ha, Akash Kumar
2016 — conf
Parallel Discord Discovery.
PAKDD (2)
Tian Huang, Yongxin Zhu, Yishu Mao, Xinyang Li, Mengyun Liu, Yafei Wu, Yajun Ha, Gillian Dobbie
2016 — conf
Unified data authenticated encryption for vehicular communication.
MWSCAS
Yi Wang, Jianfeng An, Yajun Ha
2015 J jnl
A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range.
IEEE Trans. Circuits Syst. II Express Briefs
Wenfeng Zhao, Anastacia B. Alvarez, Yajun Ha
2015 C conf
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption.
ISCAS
Wenfeng Zhao, Yajun Ha, Massimo Alioto
2015 — conf
Challenges and future trends for embedded security in electric vehicular communications.
ASICON
Yi Wang, Zhiqian Hong, Jun Li, Shaobo Luo, Yajun Ha
2015 J jnl
Correlation ratio based volume image registration on GPUs.
Microprocess. Microsystems
Ang Li, Akash Kumar, Yajun Ha, Henk Corporaal
2015 J jnl
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study.
IEEE Trans. Very Large Scale Integr. Syst.
Wenfeng Zhao, Yajun Ha, Massimo Alioto
2015 B conf
ParaLaR: A parallel FPGA router based on Lagrangian relaxation.
FPL
Chin Hau Hoo, Akash Kumar, Yajun Ha
2015 J jnl
Performance and security-enhanced fuzzy vault scheme based on ridge features for distorted fingerprints.
IET Biom.
Thi Hanh Nguyen, Yi Wang, Yajun Ha, Renfa Li
2015 J jnl
Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms.
IEEE Trans. Computers
Guiyuan Jiang, Jigang Wu, Yajun Ha, Yi Wang, Jizhou Sun
2015 J jnl
TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs.
CoRR
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
2014 — conf
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor.
A-SSCC
Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang
2014 J jnl
A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kejie Huang, Yajun Ha, Rong Zhao, Akash Kumar, Yong Lian
2014 J jnl
A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yi Wang, Yajun Ha
2014 — conf
A heterogeneous platform with GPU and FPGA for power efficient high performance computing.
ISIC
Qiang Wu, Yajun Ha, Akash Kumar, Shaobo Luo, Ang Li, Shihab Mohamed
2014 — conf
FPGA-based high throughput XTS-AES encryption/decryption for storage area network.
FPT
Yi Wang, Akash Kumar, Yajun Ha
2014 A conf
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs.
DATE
Heng Yu, Rizwan Syed, Yajun Ha
2013 B conf
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm.
FPL
Chin Hau Hoo, Yajun Ha, Akash Kumar
2013 C conf
An area-efficient shuffling scheme for AES implementation on FPGA.
ISCAS
Yi Wang, Yajun Ha
2013 B conf
Criticality-based routing for FPGAS with reverse body bias switch box architectures.
FPL
Wei Ting Loke, Wenfeng Zhao, Yajun Ha
2013 — conf
Dynamic Scheduling of Imprecise-Computation Tasks on Real-Time Embedded Multiprocessors.
CSE
Heng Yu, Bharadwaj Veeravalli, Yajun Ha, Shaobo Luo
2013 B conf
FPGA based Rekeying for cryptographic key management in Storage Area Network.
FPL
Yi Wang, Yajun Ha
2013 J jnl
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network.
IEEE Trans. Circuits Syst. II Express Briefs
Yi Wang, Yajun Ha
2013 Misc conf
High Speed Video Processing Using Fine-Grained Processing on FPGA Platform.
FCCM
Zhi Ping Ang, Akash Kumar, Yajun Ha
2013 J jnl
Improved chaff point generation for vault scheme in bio-cryptosystems.
IET Biom.
Thi Hanh Nguyen, Yi Wang, Yajun Ha, Renfa Li
2013 J jnl
Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems.
IEEE Trans. Computers
Heng Yu, Yajun Ha, Bharadwaj Veeravalli
2013 A conf
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology.
ISLPED
Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez
2013 — conf
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.
ASP-DAC
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
2013 — conf
The architecture and placement algorithm for a uni-directional routing based 3D FPGA.
FPT
Junsong Hou, Heng Yu, Yajun Ha, Xin Liu
2013 — conf
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface.
FPT
Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shu Qin Ren, Khin Mi Mi Aung
2012 — conf
A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs.
IPDPS Workshops
Wei Ting Loke, Yajun Ha, Wenfeng Zhao
2012 — conf
A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters.
ARC
Wei Ting Loke, Yajun Ha
2012 J jnl
A low overhead abstract architecture for FPGA resource management.
SIGARCH Comput. Archit. News
Rizwan Syed, Yajun Ha, Bharadwaj Veeravalli
2012 — conf
Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs.
FPT
Chao Wang, Xi Li, Xuehai Zhou, Yajun Ha
2012 A conf
Power-aware FPGA technology mapping for programmable-VT architectures (abstract only).
FPGA
Wei Ting Loke, Yajun Ha
2011 C conf
A Hilbert curve-based delay fault characterization method for FPGAs.
ISCAS
Wenjuan Zhang, Yajun Ha
2010 J jnl
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage.
IEEE J. Solid State Circuits
Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha
2010 — conf
An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee.
FPT
Zhiyao Joseph Yang, Akash Kumar, Yajun Ha
2010 — conf
B*-tree based variability-aware floorplanning.
APCCAS
Wenjuan Zhang, Shefali Srivastava, Yajun Ha
2010 C conf
Communication-aware application mapping and scheduling for NoC-based MPSoCs.
ISCAS
Heng Yu, Yajun Ha, Bharadwaj Veeravalli
2010 J jnl
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Akash Kumar, Bart Mesman, Henk Corporaal, Yajun Ha
2010 A* conf
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems.
DAC
Heng Yu, Bharadwaj Veeravalli, Yajun Ha
2010 — conf
Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA.
FPT
Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan, Yajun Ha
2010 C conf
Performance-cost analyses software for H.264 Forward/Inverse Integer Transform.
International Symposium on Rapid System Prototyping
Trang T. T. Do, Thinh M. Le, Binh P. Nguyen, Yajun Ha
2010 — ed.
Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China
FPT
Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao
2010 — conf
The Optimization of Interconnection Networks in FPGAs.
Dynamically Reconfigurable Architectures
Xiaolei Chen, Yajun Ha
2010 J jnl
Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array.
IEEE Trans. Biomed. Circuits Syst.
Haiting Tian, Shakith Fernando, Hock Wei Soon, Zhang Qiang, Chunxi Zhang, Yajun Ha, Nanguang Chen
2009 — conf
A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study.
ERSA
Guolei Zhu, Heng Yu, Yajun Ha, Yingmin Wang
2009 — conf
An optimized design for serial-parallel finite field multiplication over
ASP-DAC
Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee
2009 — conf
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply.
ISSCC
Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha
2009 B conf
sFPGA2 - A scalable GALS FPGA architecture and design methodology.
FPL
Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli
2008 B conf
A low overhead fault tolerant FPGA with new connection box.
FPL
Fujie Wong, Yajun Ha
2008 Misc conf
An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects.
FCCM
Hanyu Liu, Xiaolei Chen, Yajun Ha
2008 B conf
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.
FPL
Hanyu Liu, Xiaolei Chen, Yajun Ha
2008 J jnl
Analyzing composability of applications on MPSoC platforms.
J. Syst. Archit.
Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha
2008 B conf
Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA.
FPL
Haiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang Chen
2008 — conf
Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems.
ASP-DAC
Heng Yu, Bharadwaj Veeravalli, Yajun Ha
2008 J jnl
Interference-Minimized Multipath Routing with Congestion Control in Wireless Sensor Network for High-Rate Streaming.
IEEE Trans. Mob. Comput.
Jenn-Yue Teo, Yajun Ha, Chen-Khong Tham
2008 J jnl
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.
ACM Trans. Design Autom. Electr. Syst.
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal
2008 — conf
Statistical noise margin estimation for sub-threshold combinational circuits.
ASP-DAC
Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha
2008 — conf
Tighter WCET analysis of input dependent programs with classified-cache memory architecture.
ICECS
Yanhui Li, Shakith Fernando, Heng Yu, Xiaolei Chen, Yajun Ha, Teng Tiow Tay
2008 B conf
sFPGA - A scalable switch based FPGA architecture and design methodology.
FPL
Shakith Fernando, Xiaolei Chen, Yajun Ha
2007 A* conf
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices.
DAC
Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha
2007 B conf
Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools.
FPL
Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun Ha
2007 B conf
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA.
FPL
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal
2007 A conf
V
ISLPED
Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha
2006 — conf
An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model.
ASP-DAC
Yu Pu, Yajun Ha
2006 C conf
Global Analysis of Resource Arbitration for MPSoC.
DSD
Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha
2006 — conf
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip.
ESTIMedia
Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha
2005 J jnl
An Embedded System to Support Tele-Medical Activity.
Int. J. Softw. Eng. Knowl. Eng.
Jia Hui Ng, Chaur Lih Tan, Yajun Ha
2005 Misc conf
Design of Networked Reconfigurable Encryption Engine.
FCCM
Shakith Fernando, Yajun Ha
2005 J jnl
Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11.
Int. J. Softw. Eng. Knowl. Eng.
Yung Han Tan, Arun Krishnan Thampi, Daley Joseph Sebastian, Yajun Ha
2002 B conf
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.
FPL
Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man
2002 J jnl
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
J. Supercomput.
Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Rudy Lauwereins, Hugo De Man
2001 Misc conf
A SW/HW Interface API for Java/FPGA Co-Designed Applets.
FCCM
Yajun Ha, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man
2001 B conf
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.
FPL
Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
2001 — conf
Virtual Java/FPGA interface for networked reconfiguration.
ASP-DAC
Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man
2000 C conf
A Hardware Virtual Machine for the Networked Reconfiguration.
IEEE International Workshop on Rapid System Prototyping
Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
2000 Misc conf
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
PDPTA
Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man
1999 — conf
Low-voltage high driving capability CMOS buffer used in MEMS interface circuits.
ICECS
Yajun Ha, M. F. Li, Ai Qun Liu