Yahya Jan

11 papers Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2024 J jnl
Quality-driven design of deep neural network hardware accelerators for low power CPS and IoT applications.
Microprocess. Microsystems
Yahya Jan, Lech Józwiak
2021 — conf
Quality-driven Design of Deep Neural Network Accelerators for CPS and IoT Applications.
MECO
Yahya Jan, Lech Józwiak
2014 J jnl
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding.
Microprocess. Microsystems
Yahya Jan, Lech Józwiak
2013 J jnl
Design of massively parallel hardware multi-processors for highly-demanding embedded applications.
Microprocess. Microsystems
Lech Józwiak, Yahya Jan
2013 — conf
Hardware Multi-processor Design for Highly-Demanding Applications.
ITNG
Lech Józwiak, Yahya Jan
2012 J jnl
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.
VLSI Design
Yahya Jan, Lech Józwiak
2012 J jnl
Scalable communication architectures for massively parallel hardware multi-processors.
J. Parallel Distributed Comput.
Yahya Jan, Lech Józwiak
2010 — conf
Architecture Design of Reconfigurable Accelerators for Demanding Applications.
ITNG
Lech Józwiak, Yahya Jan
2010 — conf
Quality-driven methodology for demanding accelerator design.
ISQED
Lech Józwiak, Yahya Jan
2009 — conf
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.
SAMOS
Yahya Jan, Lech Józwiak
2009 — conf
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.
ARC
Yahya Jan, Lech Józwiak