Yacoub M. El-Ziq

13 papers A* 6A 4Journal 3
YearRankTypeTitle / Venue / Authors
1992 A conf
An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan.
ITC
Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq
1990 J jnl
A Hardware Accelerator for Maze Routing.
IEEE Trans. Computers
Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq
1987 A* conf
A Hardware Accelerator for Maze Routing.
DAC
Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq
1984 A conf
Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design.
ITC
Yacoub M. El-Ziq, Hamid H. Butt
1983 A conf
A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature Analysis.
ITC
Yacoub M. El-Ziq, Hamid H. Butt
1982 J jnl
Fault Diagnosis of MOS Combinational Networks.
IEEE Trans. Computers
Yacoub M. El-Ziq, Stephen Y. H. Su
1981 A* conf
Automatic test generation for stuck-open faults in CMOS VLSI.
DAC
Yacoub M. El-Ziq
1981 A conf
Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI.
ITC
Yacoub M. El-Ziq, Richard J. Cloutier
1980 A* conf
A new test pattern generation system.
DAC
Yacoub M. El-Ziq
1979 A* conf
Testing of MOS combinational networks a procedure for efficient fault simulation and test generation.
DAC
Yacoub M. El-Ziq
1978 J jnl
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results.
IEEE Trans. Computers
Yacoub M. El-Ziq, Stephen Y. H. Su
1978 A* conf
Logic design automation of MOS combinational networks with fan-in, fan-out constraints.
DAC
Yacoub M. El-Ziq
1977 A* conf
Logic design automation of diagnosable MOS combinational logic networks.
DAC
Yacoub M. El-Ziq, Stephen Y. H. Su