Ya-Chin King - RankMe

26 papers Journal 15Unranked 11

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications. VLSI Technology and Circuits Yao-Hung Huang, Yu-Cheng Hsieh, Yu-Cheng Lin, Yue-Der Chih, Eric Wang, Jonathan Chang, Ya-Chin King, Chrong Jung Lin
2020	J	`jnl`	Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits Cheng-Xin Xue, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Wei-Hao Chen, Meng-Fan Chang, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang
2019	—	`conf`	A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. ISSCC Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, Chung-Chuan Lo, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2019	J	`jnl`	A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation. IEEE J. Solid State Circuits Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Meng-Fan Chang
2019	J	`jnl`	Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology. Sensors Chien-Ping Wang, Ying-Chun Shen, Peng-Chun Liou, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King
2019	J	`jnl`	FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems. Integr. Yu-Fan Chiang, Wei-Yu Chien, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King
2019	J	`jnl`	Self-Convergent Trimming SRAM True Random Number Generation With In-Cell Storage. IEEE J. Solid State Circuits Po-Shao Yeh, Chih-An Yang, Yi-Hong Chang, Yue-Der Chih, Chrong Jung Lin, Ya-Chin King
2018	—	`conf`	A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. ISSCC Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2017	J	`jnl`	A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. IEEE J. Solid State Circuits Zhibo Wang, Yongpan Liu, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya-Chin King, Chrong Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang
2017	J	`jnl`	A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors. IEEE J. Solid State Circuits Albert Lee, Chieh-Pu Lo, Chien-Chen Lin, Wei-Hao Chen, Kuo-Hsiang Hsu, Zhibo Wang, Fang Su, Zhe Yuan, Qi Wei, Ya-Chin King, Chrong Jung Lin, Hochul Lee, Pedram Khalili Amiri, Kang-Lung Wang, Yu Wang, Huazhong Yang, Yongpan Liu, Meng-Fan Chang
2016	—	`conf`	4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. ISSCC Yongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Chien-Chen Lin, Qi Wei, Yu Wang, Ya-Chin King, Chrong Jung Lin, Pedram Khalili, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang
2016	—	`conf`	7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell. ISSCC Chien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya-Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng-Fan Chang
2015	J	`jnl`	Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. Meng-Fan Chang, Albert Lee, Pin-Cheng Chen, Chrong Jung Lin, Ya-Chin King, Shyh-Shyuan Sheu, Tzu-Kun Ku
2015	J	`jnl`	Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations. IEEE J. Solid State Circuits Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chrong Jung Lin, Ku-Feng Lin, Yu-Der Chih, Tsung-Yung Jonathan Chang
2014	—	`conf`	19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. ISSCC Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Ku-Feng Lin, Yu-Der Chih, Sreedhar Natarajan, Tsung-Yung Jonathan Chang
2014	—	`conf`	A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips. APCCAS Meng-Fan Chang, Che-Wei Wu, Jui-Yu Hung, Ya-Chin King, Chomg-Jung Lin, Mon-Shu Ho, Chia-Cheng Kuo, Shyh-Shyuan Sheu
2014	J	`jnl`	Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. IEEE J. Solid State Circuits Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Ya-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, Yu-Der Chih
2013	J	`jnl`	A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro. IEEE J. Solid State Circuits Meng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Sue-Meng Yang, Ku-Feng Lin, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih
2013	J	`jnl`	An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. IEEE J. Solid State Circuits Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi
2012	—	`conf`	A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. ISSCC Meng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih
2011	—	`conf`	An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. ISSCC Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi
2005	—	`conf`	A novel single poly-silicon EEPROM using trench floating gate. MTDT Meng-Yi Wu, Shin-Chang Feng, Ya-Chin King
2005	J	`jnl`	Gate stress effect on low temperature data retention characteristics of split-gate flash memories. Microelectron. Reliab. Ling-Chang Hu, An-Chi Kang, Eric Chen, J. R. Shih, Yao-Feng Lin, Kenneth Wu, Ya-Chin King
2005	J	`jnl`	Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion. IEEE Trans. Consumer Electron. Ying-Chieh Chuang, Shih-Fang Chen, Shi-Yu Huang, Ya-Chin King
2005	—	`conf`	Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory. MTDT Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King
2004	J	`jnl`	Reliability Evaluation and Redesign of LNA. Microelectron. Reliab. Wei-Cheng Lin, Long-Jei Du, Ya-Chin King