Xuqiang Zheng - RankMe

56 papers C 4Journal 29Unranked 22

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 61.4 Gb/s/mm Wireline Transceiver Using a 7 bit-Over-8 Lane Symmetric Correlated Coding for High-Density Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Mingche Lai, Geng Zhang, Fangxu Lv, Liquan Xiao, Xuqiang Zheng, Heng Huang, Kewei Xin, Liangyong Yuan, Ruixiao Kuai, Bolin Ren, Ruotian Yin, Guohe Zhang, Chao Fan
2025	J	`jnl`	A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process. IEICE Electron. Express Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Wenxiang Zhen, Mingche Lai, Zhi Jin, Xinyu Liu
2025	J	`jnl`	A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. IEEE J. Solid State Circuits Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu
2025	J	`jnl`	A 25 Gb/s 5.99 pJ/bit SerDes receiver with CTLE and quarter-rate adaptive loop-unrolling 5-tap DFE in 28-nm CMOS technology for wireline medium-reach interconnection. IEICE Electron. Express Zhaoyang Liu, Bao Chen, Zhanhao Wen, Xuqiang Zheng, Zedong Wang, Jiang Xu, Wenxiang Zhen
2025	J	`jnl`	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. IEEE J. Solid State Circuits Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu
2025	J	`jnl`	A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection. Microelectron. J. Zhaoyang Liu, Zhanhao Wen, Bao Chen, Jiang Xu, Zedong Wang, Xuqiang Zheng
2025	J	`jnl`	An 8-bit 1-GHz SAR ADC with charge-sharing sampling and embedded auto-zero comparator for ultra-high-speed wireline systems. IEICE Electron. Express Jiang Xu, Xuqiang Zheng, Zedong Wang, Hua Xu, Wenxiang Zhen, Xuan Guo, Xinyu Liu
2025	J	`jnl`	Ensemble network using oblique coronal MRI for Alzheimer's disease diagnosis. NeuroImage Cunhao Li, Zhongjian Gao, Xiaomei Chen, Xuqiang Zheng, Xiaoman Zhang, Chih-Yang Lin
2025	J	`jnl`	Survey of Chiplet Technology: SoC Architecture, Interconnect, EDA, and Advanced Packaging. IEEE J. Emerg. Sel. Topics Circuits Syst. Hongwei Liu, Yuan Du, Bo Pu, Guojun Yuan, Yuhang Liu, Linji Zheng, Pengchao Wang, An Yang, Yu Li, Chengming Yu, Fei Guo, Xiaoteng Zhao, Xuqiang Zheng, He Sun, Yongfu Li, Shaolin Xiang, Qinfen Hao
2024	J	`jnl`	A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process. IEICE Electron. Express Sijie Fan, Zedong Wang, Hua Xu, Hengyu Xu, Wenxiang Zhen, Xuqiang Zheng
2024	J	`jnl`	A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. Microelectron. J. Bolin Ren, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu
2024	—	`conf`	A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. VLSI Technology and Circuits Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
2024	J	`jnl`	A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. Microelectron. J. Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang
2024	J	`jnl`	A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS. IEICE Electron. Express Hua Xu, Xuqiang Zheng, Zedong Wang, Chen Cai, Wenxiang Zhen, Guojun Yuan, Qinfen Hao, Xuan Guo, Zhi Jin
2024	J	`jnl`	Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li
2023	J	`jnl`	A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu
2022	J	`jnl`	A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
2022	J	`jnl`	A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu
2021	—	`conf`	A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. ESSCIRC Chen Cai, Xuqiang Zheng, Yong Chen, DanYu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu
2021	—	`conf`	A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. ESSCIRC Jian Luan, DanYu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu
2020	J	`jnl`	A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2020	J	`jnl`	A CRNN System for Sound Event Detection Based on Gastrointestinal Sound Dataset Collected by Wearable Auscultation Devices. IEEE Access Xuqiang Zheng, Chun Zhang, Ping Chen, Kang Zhao, Hanjun Jiang, Zhiwei Jiang, Huafeng Pan, Zhihua Wang, Wen Jia
2020	J	`jnl`	A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds. IEEE Trans. Neural Networks Learn. Syst. Hongxin Wang, Jigen Peng, Xuqiang Zheng, Shigang Yue
2020	J	`jnl`	Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu
2019	J	`jnl`	A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS. IEICE Electron. Express Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu
2019	—	`conf`	A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2019	J	`jnl`	A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds. CoRR Hongxin Wang, Jigen Peng, Xuqiang Zheng, Shigang Yue
2018	J	`jnl`	A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. Microelectron. J. Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang
2018	—	`—`	Design of high-speed SerDes transceiver for chip-to-chip communications in CMOS process. Xuqiang Zheng
2017	—	`conf`	A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2017	—	`conf`	A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2017	—	`conf`	A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. MWSCAS Fangxu Lv, Xuqiang Zheng, Shuai Yuan, Ziqiang Wang, Yajun He, Chun Zhang, Zhihua Wang, Jianye Wang
2017	J	`jnl`	A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang
2017	C	`conf`	A battery-less, 255 nA quiescent current temperature sensor with voltage regulator fully powered by harvesting ambient vibrational energy. ISCAS Shiquan Fan, Liuming Zhao, Peng Wang, Ran Wei, Xuqiang Zheng, Zenghui Wang, Philip X.-L. Feng
2016	J	`jnl`	A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang
2016	—	`conf`	A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. NEWCAS Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao, Chun Zhang, Fule Li, Zhihua Wang
2016	—	`conf`	A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
2016	J	`jnl`	A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2016	—	`conf`	An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators. A-SSCC Xuqiang Zheng, Chun Zhang, Shuai Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
2015	—	`conf`	A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. CICC Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
2015	—	`conf`	A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. NEWCAS Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang
2015	—	`conf`	A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. MWSCAS Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
2015	—	`conf`	A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. ESSCIRC Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang
2015	—	`conf`	A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS. CICC Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Wen Jia, Chun Zhang, Zhihua Wang
2015	—	`conf`	A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li
2015	J	`jnl`	A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2014	J	`jnl`	A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. IEEE Trans. Circuits Syst. II Express Briefs Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang
2014	—	`conf`	A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology. CICC Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2013	—	`conf`	A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. ASICON Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang
2013	—	`conf`	A 10Gb/s analog equalizer in 0.18um CMOS. ASICON Linghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2013	—	`conf`	A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. VLSI-DAT Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang
2012	C	`conf`	A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS. ISCAS Shijie Hu, Chen Jia, Ke Huang, Chun Zhang, Xuqiang Zheng, Zhihua Wang
2012	—	`conf`	A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. MWSCAS Kunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2012	C	`conf`	A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. ISCAS Ke Huang, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee, Zhihua Wang
2012	C	`conf`	A current-to-voltage integrator using area-efficient correlated double sampling technique. ISCAS Xuqiang Zheng, Fule Li, Xuan Wang, Chun Zhang
2012	—	`conf`	A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. MWSCAS Ke Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang