Xun Jiang

18 papers A* 7A 4Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2026 A conf
TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement.
FPGA
Jiarui Wang, Runzhe Tao, Jing Mai, Xun Jiang, Shenghua Wang, Cuiliu Yang, Haoyu Jie, Kan Huang, Richard Y. Sun, Yibo Lin
2025 J jnl
A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xun Jiang, Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin
2025 A* conf
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.
DAC
Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
2025 J jnl
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.
CoRR
Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
2025 A conf
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals.
DATE
Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang
2025 J jnl
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals.
CoRR
Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang
2025 A* conf
DeepLayout: Learning Neural Representations of Circuit Placement Layout.
ICML
Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Qiang Xu, Runsheng Wang, Yibo Lin
2025 A conf
GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection.
ICCAD
Chunyuan Zhao, Jiarui Wang, Xun Jiang, Jincheng Lou, Yibo Lin
2025 J jnl
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang
2024 A* conf
CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment.
ICLR
Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2024 — conf
First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects.
VLSI Technology and Circuits
Haoran Lu, Yandong Ge, Xun Jiang, Jiacheng Sun, Wanyue Peng, Rui Guo, Ming Li, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang
2024 A* conf
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation.
DAC
Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun
2024 J jnl
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction.
CoRR
Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang
2024 A* conf
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning.
DAC
Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2024 A* conf
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing.
DAC
Jiarui Wang, Xun Jiang, Yibo Lin
2023 A* conf
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.
DAC
Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang
2023 A conf
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.
ICCAD
Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2022 — conf
FPGA-Accelerated Maze Routing Kernel for VLSI Designs.
ASP-DAC
Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang