| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2020 | J | jnl |
IEEE J. Solid State Circuits
|
| 2013 | C | conf |
ISCAS
|
| 2011 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2009 | — | conf |
ISSCC
|
| 2009 | J | jnl |
IEEE J. Solid State Circuits
|
| 2009 | J | jnl |
IEEE J. Solid State Circuits
|
| 2009 | J | jnl |
IEEE J. Solid State Circuits
|
| 2009 | C | conf |
ISCAS
|
| 2008 | — | conf |
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.
ISSCC
|
| 2008 | — | conf |
CICC
|
| 2007 | C | conf |
ISCAS
|