Xuan Zeng

301 papers A* 37A 53B 3C 19Journal 131Unranked 58
YearRankTypeTitle / Venue / Authors
2026 J jnl
Atelier: An Automated Analog Circuit Design Framework via Multiple Large Language Model-Based Agents.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinyi Shen, Zihao Chen, Ji Zhuang, Jiangli Huang, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2026 J jnl
DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM With Self-Assembled Bitcell Units and MILP-Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chuyu Wang, Xinglong Yan, Zecheng Xu, Ke Hu, Keren Zhu, Shuo Li, Fan Yang, Xuan Zeng
2026 J jnl
High-Dimensional Yield Optimization for Analog Circuits via Monte Carlo Tree Search and Self-Regressive Auto-Encoder Promoted Subspace Decomposed Gaussian Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhaoting Chen, Jianping Guo, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2026 J jnl
PigMap2: A Physical Information-Guided Technology Mapping Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cunqing Lan, Hongyang Pan, Zhiang Wang, Xuan Zeng, Fan Yang, Keren Zhu
2026 — conf
PigMap3: A Physically Aware Incremental Mapping Framework with On-the-fly Post-Layout Critical Path Tracking.
ASP-DAC
Hongyang Pan, Cunqing Lan, Zhiang Wang, Xuan Zeng, Fan Yang, Keren Zhu
2026 J jnl
Variation-aware Analog Circuit Design via Contextual Modeling and Robust Optimization.
ACM Trans. Design Autom. Electr. Syst.
Jiangli Huang, Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2026 J jnl
White-Box Op-Amp Design via Human-Mimicking Reasoning.
CoRR
Zihao Chen, Jiayin Wang, Ziyi Sun, Ji Zhuang, Jinyi Shen, Xiaoyue Ke, Li Shang, Xuan Zeng, Fan Yang
2025 J jnl
APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuyang Zhao, Tianning Gao, Zheng Wu, Zhaori Bi, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025 J jnl
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinyi Shen, Fan Yang, Li Shang, Changhao Yan, Zhaori Bi, Dian Zhou, Xuan Zeng
2025 J jnl
Adaptive ILT via Multi-Level Lithography Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng
2025 J jnl
An Efficient Placement Speedup Technique Based on Graph Signal Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2025 J jnl
AnalogSeeker: An Open-source Foundation Language Model for Analog Circuit Design.
CoRR
Zihao Chen, Ji Zhuang, Jinyi Shen, Xiaoyue Ke, Xinyi Yang, Mingjie Zhou, Zhuoyao Du, Xu Yan, Zhouyang Wu, Zhenyu Xu, Jiangli Huang, Li Shang, Xuan Zeng, Fan Yang
2025 A conf
BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-LayoutSimulation.
ICCAD
Haoyang Sang, Changhao Yan, Zhaori Bi, Keren Zhu, Xuan Zeng
2025 A conf
DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement.
DATE
Chuyu Wang, Ke Hu, Fan Yang, Keren Zhu, Xuan Zeng
2025 A conf
ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis.
DATE
Hongyang Pan, Keren Zhu, Fan Yang, Zhufei Chu, Xuan Zeng
2025 J jnl
Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit.
ACM Trans. Design Autom. Electr. Syst.
Xingwei Feng, Yifan Xu, Zhangcheng Huang, Wuyi Xu, Zhaori Bi, Fan Yang, Xuan Zeng, Ye Lu
2025 A conf
INTO-OA: Interpretable Topology Optimization for Operational Amplifiers.
DATE
Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2025 A conf
LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models.
ICCAD
Zhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025 A* conf
Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space Exploration.
DAC
Xuyang Zhao, Yiyang Zhao, Zheng Wu, Tianning Gao, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2025 A* conf
MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing.
DAC
Wangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu, Zhaori Bi, Dian Zhou, Xuan Zeng
2025 A conf
NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction.
ICCAD
Yuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025 A* conf
New Time-Domain Preconditioners for HB Jacobian of RF Circuits.
DAC
Chenyi Tan, Yangfeng Su, Fan Yang, Xuan Zeng
2025 J jnl
Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zheng Wu, Jinyi Shen, Xiaoling Yi, Li Shang, Fan Yang, Xuan Zeng
2025 J jnl
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis.
ACM Trans. Design Autom. Electr. Syst.
Hongyang Pan, Keren Zhu, Fan Yang, Xuan Zeng, Sen Liu, Yong Xiao, Yun Shao, Zhufei Chu
2025 J jnl
Robust analog/RF circuit design via Cycle-Consistent Generative Adversarial Networks.
Integr.
Nanlin Guo, Jun Tao, Xuan Zeng, Xin Li
2025 J jnl
SMP-RCR: A Sparse Multipoint Moment Matching Method for RC Reduction.
CoRR
Siyuan Yin, Yuncheng Xu, Lin Liu, Fan Yang, Xuan Zeng, Chengtao An, Yangfeng Su
2025 A conf
Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search.
ICCAD
Yiyang Zhao, Xuyang Zhao, Zhaori Bi, Ming Zhu, Qiwei Zhan, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2025 J jnl
The Power of Graph Signal Processing for Chip Placement Acceleration.
CoRR
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2025 J jnl
VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aidong Zhao, Ruiyu Lyu, Xuyang Zhao, Zhaori Bi, Fan Yang, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng
2025 J jnl
pPIRW: An Efficient and Accurate Precalculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhixuan Dong, Longlong Yang, Cuiyang Ding, Changhao Yan, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2024 A conf
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping.
DATE
Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, Fan Yang, Xuan Zeng, Zhufei Chu
2024 B conf
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper).
ASPDAC
Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2024 A conf
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis.
ICCAD
Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024 J jnl
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis.
CoRR
Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024 A* conf
Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model.
DAC
Zihao Chen, Jiangli Huang, Yiting Liu, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng
2024 B conf
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing.
ASPDAC
Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng
2024 J jnl
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tianchen Gu, Wangzhen Li, Aidong Zhao, Zhaori Bi, Xudong Li, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng
2024 A conf
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data.
DATE
Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng
2024 J jnl
D
ACM Trans. Design Autom. Electr. Syst.
Aidong Zhao, Tianchen Gu, Zhaori Bi, Fan Yang, Changhao Yan, Xuan Zeng, Zixiao Lin, Wenchuang Walter Hu, Dian Zhou
2024 A* conf
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration.
DAC
Handa Sun, Zhaori Bi, Wenning Jiang, Ye Lu, Changhao Yan, Fan Yang, Wenchuang Hu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2024 A* conf
Efficient ILT via Multigrid-Schwartz Method.
DAC
Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Dian Zhou, Xuan Zeng
2024 J jnl
Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 A conf
Exploring High-dimensional Search Space via Voronoi Graph Traversing.
UAI
Aidong Zhao, Xuyang Zhao, Tianchen Gu, Zhaori Bi, Xinwei Sun, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2024 J jnl
GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lihao Liu, Fan Yang, Li Shang, Xuan Zeng
2024 A* conf
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing.
DAC
Tianchen Gu, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng
2024 J jnl
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions.
IEEE Trans. Very Large Scale Integr. Syst.
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2024 J jnl
Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 B conf
MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier.
ASPDAC
Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng
2024 J jnl
Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiarui Bao, Jinxin Zhang, Zhangcheng Huang, Zhaori Bi, Xingwei Feng, Xuan Zeng, Ye Lu
2024 A conf
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement.
ICCAD
Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu
2024 J jnl
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement.
CoRR
Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu
2024 J jnl
ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuyang Zhao, Tianning Gao, Aidong Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2024 A conf
Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis.
ICCAD
Ruiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2024 A conf
The Power of Graph Signal Processing for Chip Placement Acceleration.
ICCAD
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2024 J jnl
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation.
ACM Trans. Design Autom. Electr. Syst.
Nanlin Guo, Fulin Peng, Jiahe Shi, Fan Yang, Jun Tao, Xuan Zeng
2024 J jnl
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2024 A conf
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling.
DATE
Tianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, Xuan Zeng
2023 J jnl
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Biao He, Shuhan Zhang, Yifan Wang, Tianning Gao, Fan Yang, Changhao Yan, Dian Zhou, Zhaori Bi, Xuan Zeng
2023 J jnl
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping.
CoRR
Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, Fan Yang, Xuan Zeng, Zhufei Chu
2023 J jnl
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography.
J. Comput. Phys.
Cuiyang Ding, Yijing Zhou, Wei Cai, Xuan Zeng, Changhao Yan
2023 J jnl
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiangli Huang, Chuyu Wang, Yuyang Yan, Cong Tao, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2023 A* conf
Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning.
DAC
Jinxin Zhang, Jiarui Bao, Zhangcheng Huang, Xuan Zeng, Ye Lu
2023 A conf
Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search.
DATE
Zihao Chen, Fan Yang, Li Shang, Xuan Zeng
2023 J jnl
Automatic Op-Amp Generation From Specification to Layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jialin Lu, Liangbo Lei, Jiangli Huang, Fan Yang, Li Shang, Xuan Zeng
2023 J jnl
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhengqi Gao, Fa Wang, Jun Tao, Yangfeng Su, Xuan Zeng, Xin Li
2023 J jnl
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid.
ACM Trans. Design Autom. Electr. Syst.
Chunqiao Li, Chengtao An, Fan Yang, Xuan Zeng
2023 A* conf
Efficient ILT via Multi-level Lithography Simulation.
DAC
Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng
2023 A* conf
FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display.
DAC
Chengtao An, Chunqiao Li, Xiangqi Li, Yangfeng Su, Fan Yang, Xuan Zeng
2023 J jnl
GraphPlanner: Floorplanning with Graph Neural Network.
ACM Trans. Design Autom. Electr. Syst.
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2023 J jnl
High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization.
IEEE Trans. Circuits Syst. II Express Briefs
Jialin Lu, Yijie Li, Fan Yang, Li Shang, Xuan Zeng
2023 A conf
Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System.
ICCAD
Ruiyao Pu, Yiwei Sun, Pei-Hsin Ho, Fan Yang, Li Shang, Xuan Zeng
2023 — conf
TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning.
ISQED
Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng
2023 J jnl
Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunqiao Li, Chengtao An, Zhengqi Gao, Fan Yang, Yangfeng Su, Xuan Zeng
2023 A* conf
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.
DAC
Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi, Xudong Li, Changhao Yan, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng
2022 C conf
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.
ISCAS
Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, Xuan Zeng
2022 A conf
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions.
ICCAD
Longlong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng
2022 — conf
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.
ASP-DAC
Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou
2022 J jnl
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions.
SIAM J. Sci. Comput.
Cuiyang Ding, Changhao Yan, Xuan Zeng, Wei Cai
2022 C conf
Adversarial Sample Generation for Lithography Hotspot Detection.
ISCAS
Shuyuan Sun, Yiyang Jiang, Fan Yang, Xuan Zeng
2022 J jnl
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2022 A* conf
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling.
DAC
Xiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2022 J jnl
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaodong Wang, Changhao Yan, Yuzhe Ma, Bei Yu, Fan Yang, Dian Zhou, Xuan Zeng
2022 J jnl
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jun Tao, Handi Yu, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2022 A conf
Efficient Hotspot Detection via Graph Neural Network.
DATE
Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, Xuan Zeng
2022 J jnl
Efficient Layout Hotspot Detection via Neural Architecture Search.
ACM Trans. Design Autom. Electr. Syst.
Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng
2022 J jnl
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2022 J jnl
Faster Region-Based Hotspot Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Fan Yang, Xuan Zeng, Bei Yu
2022 A* conf
Floorplanning with graph attention.
DAC
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2022 J jnl
Hotspot Detection via Attention-Based Deep Layout Metric Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, Bei Yu
2022 J jnl
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative.
IEEE J. Biomed. Health Informatics
Yifan Wang, Zhaori Bi, Yuxue Xie, Tao Wu, Xuan Zeng, Shuang Chen, Dian Zhou
2022 — conf
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
MLCAD
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2022 C conf
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing.
ISCAS
Hao Jiang, Fan Yang, Changhao Yan, Xuan Zeng
2022 A conf
Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding.
DATE
Jialin Lu, Liangbo Lei, Fan Yang, Li Shang, Xuan Zeng
2021 — conf
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits.
ASICON
Jiahui Hu, Changhao Yan, Chao Guo, Ronggui Jiang, Dian Zhou, Xuan Zeng
2021 J jnl
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2021 — conf
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.
ASP-DAC
Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 A conf
Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression.
ICCAD
Cheng Zeng, Fan Yang, Xuan Zeng
2021 J jnl
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis.
CoRR
Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
2021 J jnl
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble.
CoRR
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 A conf
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays.
DATE
Yue Shen, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2021 A* conf
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization.
DAC
Jialin Lu, Liangbo Lei, Fan Yang, Changhao Yan, Xuan Zeng
2021 — conf
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits.
ASP-DAC
Zhengqi Gao, Zihao Chen, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng
2021 C conf
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process.
ISCAS
Jiangli Huang, Shuhan Zhang, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 — conf
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling.
ASICON
Yingqi Li, Fan Yang, Changhao Yan, Xuan Zeng
2021 J jnl
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng
2021 — conf
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure.
ASICON
Yan Wang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 A conf
Hotspot Detection via Multi-task Learning and Transformer Encoder.
ICCAD
Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong
2021 J jnl
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
CoRR
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 A* conf
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.
DAC
Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng
2021 A conf
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning.
ICCAD
Hao Geng, Fan Yang, Xuan Zeng, Bei Yu
2020 C conf
A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis.
ISCAS
Jialin Lu, Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
2020 A* conf
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis.
DAC
Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
2020 A conf
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling.
DATE
Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2020 C conf
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM.
ISCAS
Binbin Liu, Fan Yang, Dian Zhou, Xuan Zeng
2020 A* conf
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
DAC
Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2020 J jnl
Analog/RF Post-silicon Tuning via Bayesian Optimization.
ACM Trans. Design Autom. Electr. Syst.
Renjian Pan, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2020 — conf
Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits.
ASP-DAC
Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
2020 J jnl
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhengqi Gao, Jun Tao, Dian Zhou, Xuan Zeng
2020 J jnl
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2020 J jnl
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fulin Peng, Handi Yu, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2020 A conf
Hotspot Detection via Attention-based Deep Layout Metric Learning.
ICCAD
Hao Geng, Haoyu Yang, Lu Zhang, Jin Miao, Fan Yang, Xuan Zeng, Bei Yu
2020 J jnl
Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic.
IEEE Trans. Circuits Syst. Video Technol.
Yufeng Li, Yan Li, I-Chyn Wey, Deqiang Cheng, Fan Yang, Xuan Zeng, Jie Chen
2020 C conf
Learning Low-Rank Structured Sparsity in Recurrent Neural Networks.
ISCAS
Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng
2020 C conf
Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior.
ISCAS
Jiahe Shi, Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng
2020 J jnl
Nonlinear CNN: improving CNNs with quadratic convolutions.
Neural Comput. Appl.
Yiyang Jiang, Fan Yang, Hengliang Zhu, Dian Zhou, Xuan Zeng
2020 J jnl
Projection based Active Gaussian Process Regression for Pareto Front Modeling.
CoRR
Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng
2019 J jnl
A single event upset tolerant latch with parallel nodes.
IEICE Electron. Express
Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu
2019 J jnl
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition.
IEEE Trans. Very Large Scale Integr. Syst.
Xiang Ge, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou
2019 A conf
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
DATE
Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2019 J jnl
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse.
ACM Trans. Reconfigurable Technol. Syst.
Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou
2019 A* conf
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
DAC
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu
2019 J jnl
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
CoRR
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu
2019 J jnl
An inverter chain with parallel output nodes for eliminating single-event transient pulse.
IEICE Electron. Express
Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu
2019 A conf
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network.
DATE
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2019 J jnl
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network.
CoRR
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2019 A* conf
Efficient Layout Hotspot Detection via Binarized Residual Neural Network.
DAC
Yiyang Jiang, Fan Yang, Hengliang Zhu, Bei Yu, Dian Zhou, Xuan Zeng
2019 A conf
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network.
ICCAD
Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng
2019 A* conf
Faster Region-based Hotspot Detection.
DAC
Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Xuan Zeng, Bei Yu
2019 J jnl
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2019 — conf
Learning Sparse Patterns in Deep Neural Networks.
ASICON
Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng
2019 — conf
Parallel Global Placement on CPU via Parallel Reduction.
ASICON
Huaidong Gao, Fan Yang, Dian Zhou, Xuan Zeng
2019 J jnl
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.
IEEE Trans. Very Large Scale Integr. Syst.
Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng
2019 — conf
Scheduling Algorithm Based on System of Difference Constraints Using Network Flow.
ASICON
Hao Jiang, Yang Fan, Xuan Zeng
2018 J jnl
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.
IEICE Electron. Express
Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu
2018 A* conf
A general graph based pessimism reduction framework for design optimization of timing closure.
DAC
Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2018 J jnl
A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence.
Biomed. Signal Process. Control.
Qingxue Zhang, Dian Zhou, Xuan Zeng
2018 J jnl
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wenlong Lyu, Pan Xue, Fan Yang, Changhao Yan, Zhiliang Hong, Xuan Zeng, Dian Zhou
2018 J jnl
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis.
ACM Trans. Design Autom. Electr. Syst.
Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng
2018 A conf
An efficient data reuse strategy for multi-pattern data access.
ICCAD
Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou
2018 A* conf
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
ICML
Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2018 J jnl
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng
2018 J jnl
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mengshuo Wang, Wenlong Lv, Fan Yang, Changhao Yan, Wei Cai, Dian Zhou, Xuan Zeng
2018 J jnl
Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Yan Li, Yufeng Li, Jie Han, Jianhao Hu, Fan Yang, Xuan Zeng, Bruce F. Cockburn, Jie Chen
2018 J jnl
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hengliang Zhu, Feng Hu, Hao Zhou, David Z. Pan, Dian Zhou, Xuan Zeng
2018 J jnl
Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.
IEEE J. Solid State Circuits
Yan Li, Yufeng Li, I-Chyn Wey, Jianhao Hu, Fan Yang, Xuan Zeng, Xiaoxue Jiang, Jie Chen
2018 A* conf
Multi-objective bayesian optimization for analog/RF circuit synthesis.
DAC
Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2018 J jnl
Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.
IEICE Electron. Express
Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng
2018 J jnl
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng
2018 — conf
Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach.
ISVLSI
Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li, Xuan Zeng
2018 J jnl
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method.
IEEE Trans. Very Large Scale Integr. Syst.
Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, Xuan Zeng
2017 J jnl
A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG.
IEEE Access
Qingxue Zhang, Xuan Zeng, Wenchuang Walter Hu, Dian Zhou
2017 J jnl
A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping.
IEEE Trans. Biomed. Eng.
Qingxue Zhang, Dian Zhou, Xuan Zeng
2017 — conf
A Novel N-Retry Transactional Memory Model for Multi-Thread Programming.
ISPA/IUCC
Kun Lu, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017 C conf
A grid-based detailed routing algorithm for advanced 1D process.
ISCAS
Ye Zhang, Fan Yang, Dian Zhou, Xuan Zeng, Xiangdong Hu
2017 J jnl
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst.
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng
2017 — conf
An efficient algorithm for stencil planning and optimization in E-beam lithography.
ASP-DAC
Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017 J jnl
An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer.
Sci. China Inf. Sci.
Guanming Huang, Donesh Gillin, Dian Zhou, Jin Liu, Xuan Zeng, Po-Yu Kuo
2017 A conf
An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid.
DATE
Chao Yan, Hengliang Zhu, Dian Zhou, Xuan Zeng
2017 J jnl
C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Zeng, Hengliang Zhu, Xuan Zeng, Dian Zhou, Ruey-Wen Liu, Xin Li
2017 A* conf
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation.
DAC
Jun Tao, Handi Yu, Dian Zhou, Yangfeng Su, Xuan Zeng, Xin Li
2017 A* conf
Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits.
DAC
Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu
2017 J jnl
Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jincheng Su, Fan Yang, Xuan Zeng, Dian Zhou, Jie Chen
2017 C conf
Efficient SVM-based hotspot detection using spectral clustering.
ISCAS
Fan Yang, Charles C. Chiang, Xuan Zeng, Dian Zhou
2017 C conf
Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis.
ISCAS
Shuhan Zhang, Fan Yang, Xuan Zeng, Dian Zhou, Shun Li, Xiangdong Hu
2017 — conf
Hear the heart: Daily cardiac health monitoring using Ear-ECG and machine learning.
UEMCON
Qingxue Zhang, Dian Zhou, Xuan Zeng
2017 J jnl
HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications.
IEEE Access
Qingxue Zhang, Dian Zhou, Xuan Zeng
2017 J jnl
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Mengshuo Wang, Changhao Yan, Xin Li, Dian Zhou, Xuan Zeng
2017 A conf
Impact of circuit-level non-idealities on vision-based autonomous driving systems.
ICCAD
Handi Yu, Changhao Yan, Xuan Zeng, Xin Li
2017 J jnl
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fan Yang, Subarna Sinha, Charles C. Chiang, Xuan Zeng, Dian Zhou
2017 C conf
Layout decomposition for hybrid E-beam and DSA double patterning lithography.
ISCAS
Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu
2017 C conf
Methodologies for layout decomposition and mask optimization: A systematic review.
VLSI-SoC
Yuzhe Ma, Xuan Zeng, Bei Yu
2017 — conf
Network flow based cut redistribution and insertion for advanced 1D layout design.
ASP-DAC
Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017 J jnl
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method.
ACM Trans. Design Autom. Electr. Syst.
Zhaori Bi, Dian Zhou, Sheng-Guo Wang, Xuan Zeng
2017 — conf
Parallel sparse LU decomposition using FPGA with an efficient cache architecture.
ASICON
Xiang Ge, Hengliang Zhu, Fan Yang, Lingli Wang, Xuan Zeng
2017 — conf
PulsePrint: Single-arm-ECG biometric human identification using deep learning.
UEMCON
Qingxue Zhang, Dian Zhou, Xuan Zeng
2017 A conf
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
DATE
Wenlong Lv, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2016 J jnl
A Memristor Crossbar-Based Computation Scheme with High Precision.
CoRR
Junyi Li, Fulin Peng, Fan Yang, Xuan Zeng
2016 A conf
A novel unified dummy fill insertion framework with SQP-based optimization method.
ICCAD
Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2016 J jnl
A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.
Sci. China Inf. Sci.
Minghua Li, Guanming Huang, Xiulong Wu, Liuxi Qian, Xuan Zeng, Dian Zhou
2016 — conf
Algorithms in ParAFEMImp: A Parallel and Wideband Impedance Extraction Program for Complicated 3-D Geometries.
BigDataSecurity/HPSC/IDS
Tao Cui, Junqing Chen, Hengliang Zhu, Xuan Zeng
2016 J jnl
An aggregating based model order reduction method for power grids.
Integr.
Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng
2016 — conf
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation.
ASP-DAC
Chenjie Yang, Fan Yang, Xuan Zeng, Dian Zhou
2016 J jnl
Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Changhai Liao, Jun Tao, Handi Yu, Zhangwen Tang, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2016 A conf
Efficient Memory Partitioning for Parallel Data Access via Data Reuse.
FPGA
Jincheng Su, Fan Yang, Xuan Zeng, Dian Zhou
2016 J jnl
Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li
2016 A conf
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
DATE
Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng, Dian Zhou
2016 A* conf
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression.
DAC
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li
2016 A* conf
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits.
DAC
Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li
2016 A conf
Efficient spatial variation modeling via robust dictionary learning.
DATE
Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li
2016 A conf
Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation.
ICCAD
Handi Yu, Jun Tao, Changhai Liao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
2016 C conf
Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit.
ISCAS
Zhelun Yu, Jincheng Su, Fan Yang, Yangfeng Su, Xuan Zeng, Dian Zhou, Weiping Shi
2016 J jnl
Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jun Tao, Changhai Liao, Xuan Zeng, Xin Li
2016 C conf
High-speed link verification based on statistical inference.
ISCAS
Xuan Zeng, Chenlei Fang, Qicheng Huang, Fan Yang, Dian Zhou, Wei Cai, Weiping Shi
2016 J jnl
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng
2015 — conf
Analog circuit performance bound estimation based on extreme value theory.
MWSCAS
Minghua Li, Zhaori Bi, Dian Zhou, Xuan Zeng
2015 J jnl
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework.
IEEE Trans. Very Large Scale Integr. Syst.
Liuxi Qian, Zhaori Bi, Dian Zhou, Xuan Zeng
2015 J jnl
Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hengliang Zhu, Yuanzhe Wang, Frank Liu, Xin Li, Xuan Zeng, Peter Feldmann
2015 A conf
Efficient bit error rate estimation for high-speed link by Bayesian model fusion.
DATE
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li, Chenjie Gu
2015 A* conf
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits.
DAC
Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li
2015 J jnl
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst.
Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng
2015 — conf
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
ASP-DAC
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou
2015 J jnl
MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiao Li, Fan Yang, Dake Wu, Zhenya Zhou, Xuan Zeng
2015 — conf
Machine learning and pattern matching in physical design.
ASP-DAC
Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng
2015 J jnl
Multi-parameter clock skew scheduling.
Integr.
Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng
2015 — conf
PGMOR: An Efficient Model Order Reduction Method for Power Grids.
CAD/Graphics
Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng
2015 J jnl
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method.
Integr.
Zhenyu Wu, Changhao Yan, Xuan Zeng, Sheng-Guo Wang
2015 — conf
SIPredict: Efficient post-layout waveform prediction via System Identification.
ASP-DAC
Qicheng Huang, Xiao Li, Fan Yang, Xuan Zeng, Xin Li
2014 A* conf
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits.
DAC
Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li
2014 J jnl
Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Xingbao Zhou, Fan Yang, Hai Zhou, Min Gong, Hengliang Zhu, Ye Zhang, Xuan Zeng
2014 J jnl
Integrated Algorithm for 3-D IC Through-Silicon Via Assignment.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaodong Liu, Gary K. Yeap, Jun Tao, Xuan Zeng
2014 A conf
Recovery-based resilient latency-insensitive systems.
DATE
Yuankai Chen, Xuan Zeng, Hai Zhou
2013 J jnl
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks.
SIAM J. Sci. Comput.
Changhao Yan, Wei Cai, Xuan Zeng
2013 — conf
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement.
ASICON
Liuxi Qian, Dian Zhou, Xuan Zeng, Fan Yang, Shengguo Wang
2013 — conf
A practical method for auto-design and optimization of DC-DC buck converter.
ASICON
Guanming Huang, Dian Zhou, Xuan Zeng, Shengguo Wang
2013 J jnl
An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guanming Huang, Liuxi Qian, Siwat Saibua, Dian Zhou, Xuan Zeng
2013 J jnl
An efficient method for gradient-aware dummy fill synthesis.
Integr.
Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2013 — conf
FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp.
ASICON
Minghua Li, Dian Zhou, Sheng-Guo Wang, Xuan Zeng
2013 — conf
Graph Steiner tree construction and its routing applications.
ASICON
Jun Dong, Hengliang Zhu, Min Xie, Xuan Zeng
2013 A conf
Layout decomposition with pairwise coloring for multiple patterning lithography.
ICCAD
Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng
2013 — conf
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design.
ASICON
Zhaori Bi, Wei Li, Dian Zhou, Xuan Zeng, Sheng-Guo Wang
2013 J jnl
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Li, Dian Zhou, Minghua Li, Binh P. Nguyen, Xuan Zeng
2013 — conf
Oscillator phase noise verification accounting for process variations.
ASICON
Liuxi Qian, Dian Zhou, Xuan Zeng, Shengguo Wang
2013 J jnl
Post-routing layer assignment for double patterning with timing critical paths consideration.
Integr.
Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng
2013 J jnl
SmipRef: An efficient method for multi-domain clock skew scheduling.
Integr.
Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng
2012 A* conf
AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits.
DAC
Yangfeng Su, Fan Yang, Xuan Zeng
2012 A* conf
Improved tangent space based distance metric for accurate lithographic hotspot classification.
DAC
Jing Guo, Fan Yang, Subarna Sinha, Charles C. Chiang, Xuan Zeng
2012 J jnl
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yanling Zhi, Wai-Shing Luk, Yi Wang, Changhao Yan, Xuan Zeng
2011 A conf
A new method for multiparameter robust stability distribution analysis of linear analog circuits.
ICCAD
Changhao Yan, Sheng-Guo Wang, Xuan Zeng
2011 — conf
A practical method for multi-domain clock skew optimization.
ASP-DAC
Yanling Zhi, Hai Zhou, Xuan Zeng
2011 A conf
An efficient algorithm for multi-domain clock skew scheduling.
DATE
Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng
2011 A* conf
An integrated algorithm for 3D-IC TSV assignment.
DAC
Xiaodong Liu, Yifan Zhang, Gary K. Yeap, Xuan Zeng
2011 J jnl
Binning Optimization for Transparently-Latched Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng
2011 J jnl
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2011 J jnl
Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Zyad Hassan, Nicholas Allec, Fan Yang, Li Shang, Robert P. Dick, Xuan Zeng
2011 — conf
Low power discrete voltage assignment under clock skew scheduling.
ASP-DAC
Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng
2011 — conf
Parallel cross-layer optimization of high-level synthesis and physical design.
ASP-DAC
James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng
2011 — conf
Post-routing layer assignment for double patterning.
ASP-DAC
Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng
2011 J jnl
Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations.
IEICE Trans. Electron.
Zhihua Gui, Fan Yang, Xuan Zeng
2010 J jnl
A Wavelet-Collocation-Based Trajectory Piecewise-Linear Algorithm for Time-Domain Model-Order Reduction of Nonlinear Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ke Zong, Fan Yang, Xuan Zeng
2010 A conf
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits.
DATE
Xiaoda Pan, Fan Yang, Xuan Zeng, Yangfeng Su
2010 A* conf
Global routing and track assignment for flip-chip designs.
DAC
Xiaodong Liu, Yifan Zhang, Gary K. Yeap, Chunlei Chu, Jian Sun, Xuan Zeng
2010 — conf
Intel LVS logic as a combinational logic paradigm in CNT technology.
NANOARCH
Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H.-S. Philip Wong
2010 J jnl
Multicore Parallelization of Min-Cost Flow for CAD Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
2010 J jnl
NHAR: A non-homogeneous Arnoldi method for fast simulation of RCL circuits with a large number of ports.
Int. J. Circuit Theory Appl.
Xuan Zeng, Fan Yang, Yangfeng Su, Wei Cai
2010 J jnl
Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou
2009 J jnl
A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Xu Luo, Fan Yang, Xuan Zeng, Jun Tao, Hengliang Zhu, Wei Cai
2009 A conf
Binning optimization based on SSTA for transparently-latched circuits.
ICCAD
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
2009 J jnl
Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng
2009 J jnl
Generalized Stochastic Collocation Method for Variation-Aware Capacitance Extraction of Interconnects Considering Arbitrary Random Probability.
IEICE Trans. Electron.
Hengliang Zhu, Xuan Zeng, Xu Luo, Wei Cai
2009 C conf
Incremental Circuit Simulation Analysis for Design Modification and Verification.
ISCAS
Tracey Y. Zhou, Dian Zhou, Xuan Zeng
2009 J jnl
Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qiang Fu, Wai-Shing Luk, Jun Tao, Xuan Zeng, Wei Cai
2009 A* conf
Multicore parallel min-cost flow algorithm for CAD applications.
DAC
Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
2009 A* conf
Provably good and practically efficient algorithms for CMP dummy fill.
DAC
Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2009 — conf
Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method.
ASP-DAC
Duo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng
2009 A* conf
Statistical reliability analysis under process variation and aging effects.
DAC
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng
2008 — conf
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
ISQED
Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai
2008 J jnl
Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Wei Cai
2008 — conf
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.
ISQED
Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng
2008 J jnl
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng
2008 A* conf
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
DAC
Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni
2007 J jnl
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng
2007 A conf
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.
DATE
Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou
2007 A conf
Parameterized model order reduction via a two-directional Arnoldi process.
ICCAD
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng
2007 C conf
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.
ISCAS
Fan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou
2007 — conf
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic.
ASP-DAC
Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, Xuan Zeng
2007 — conf
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.
ASP-DAC
Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles C. Chiang
2007 — conf
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.
ASP-DAC
Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng
2006 — conf
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.
APCCAS
Hengliang Zhu, Xuan Zeng, Wei Cai, Dian Zhou
2006 C conf
A one-shot projection method for interconnects with process variations.
ISCAS
Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles C. Chiang
2006 A conf
Time domain model order reduction by wavelet collocation method.
DATE
Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles C. Chiang
2005 — conf
A novel wavelet method for noise analysis of nonlinear circuits.
ASP-DAC
Xuan Zeng, Bang Liu, Jun Tao, Charles C. Chiang, Dian Zhou
2005 — conf
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits.
ASP-DAC
Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles C. Chiang, Dian Zhou
2005 — conf
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.
ISCAS (1)
Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
2005 J jnl
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
2004 — conf
Analog circuit behavioral modeling via wavelet collocation method with auto-companding.
ASP-DAC
Jian Wang, Jun Tao, Xuan Zeng, Charles C. Chiang, Dian Zhou
2004 A conf
Direct Nonlinear Order Reduction with Variational Analysis.
DATE
Lihong Feng, Xuan Zeng, Charles C. Chiang, Dian Zhou, Qiang Fang
2004 — conf
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.
ISCAS (5)
Jian Wang, Xuan Zeng, Wei Cai, Charles C. Chiang, Jiarong Tong, Dian Zhou
2004 A conf
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits.
ICCAD
Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles C. Chiang, Dian Zhou
2004 A conf
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.
DATE
Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles C. Chiang
2004 — conf
Two-sided projection method in variational equation model order reduction of nonlinear circuits.
ISCAS (4)
Lihong Feng, Xuan Zeng, Jiarong Tong, Charles C. Chiang, Dian Zhou
2003 — conf
An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method.
ISCAS (4)
Xuan Zeng, Sheng Huang, Yangfeng Su, Dian Zhou
2003 — conf
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation.
ISCAS (3)
Xuan Zeng, Jun Tao, Yangfeng Su, Wenbing Chen, Dian Zhou
2003 J jnl
Behavioral modeling for analog system-level simulation by wavelet collocation method.
IEEE Trans. Circuits Syst. II Express Briefs
Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling, Wei Cai
2003 A conf
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing.
ICCAD
Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
2002 — conf
Wavelet method for high-speed clock tree simulation.
ISCAS (1)
Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
2001 — conf
A wavelet balance approach for steady-state analysis of nonlinear circuits.
ISCAS (3)
Xin Li, Bo Hu, Xieting Ling, Xuan Zeng
2001 — conf
Automatic clock tree design with IPs in the system.
ISCAS (5)
Wei Li, Dian Zhou, Haksu Kim, Xuan Zeng
2001 A conf
Behavioral Modeling of Analog Circuits by Wavelet Collocation Method.
ICCAD
Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
2000 C conf
Parasitic and mismatch modeling for optimal stack generation [in CMOS].
ISCAS
Xuan Zeng, Mingyuan Li, Wenqing Zhao, Pushan Tang, Dian Zhou
1999 — conf
A constraint-based placement refinement method for CMOS analog cell layout.
ISCAS (6)
Xuan Zeng, J. Guan, Wenqing Zhao, Pushan Tang, Dian Zhou
1999 — conf
Buffer insertion for clock delay and skew minimization.
ISPD
Xuan Zeng, Dian Zhou, Wei Li