Xuan-Lun Huang

17 papers A 2B 2Misc 1Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Scalable Photonic Computer Solving the Subset Sum Problem.
CoRR
Xiao Yun Xu, Xuan-Lun Huang, Zhan-Ming Li, Jun Gao, Zhi-Qiang Jiao, Yao Wang, Ruo-Jing Ren, H. P. Zhang, Xian-Min Jin
2015 J jnl
Design and Implementation of an FPGA-Based Data/Timing Formatter.
J. Electron. Test.
Yu-Yi Chen, Jiun-Lang Huang, Terry Kuo, Xuan-Lun Huang
2014 — conf
FPGA-Based Subset Sum Delay Lines.
ATS
Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang
2013 J jnl
A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS.
IEEE J. Solid State Circuits
Ming-Feng Huang, Ming-Ching Kuo, Tzu-Yi Yang, Xuan-Lun Huang
2013 B conf
A mutual characterization based SAR ADC self-testing technique.
ETS
H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang
2013 A conf
An IDDQ-based source driver IC design-for-test technique.
ICCAD
S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang
2012 — conf
A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC.
Asian Test Symposium
Y.-H. Chou, Jiun-Lang Huang, Xuan-Lun Huang
2012 J jnl
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration.
J. Electron. Test.
Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai
2011 B conf
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager.
ETS
Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai
2011 — conf
A self-testing and calibration method for embedded successive approximation register ADC.
ASP-DAC
Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
2011 J jnl
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling.
IEEE Trans. Very Large Scale Integr. Syst.
Xuan-Lun Huang, Jiun-Lang Huang
2011 J jnl
Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs.
J. Electron. Test.
Xuan-Lun Huang, Ping-Ying Kang, Yuan-Chi Yu, Jiun-Lang Huang
2010 A conf
A robust ADC code hit counting technique.
DATE
Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang
2010 Misc conf
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling.
VTS
Xuan-Lun Huang, Jiun-Lang Huang
2009 — conf
An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing.
Asian Test Symposium
Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang
2009 — conf
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input.
ASP-DAC
Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang
2006 — conf
A routability constrained scan chain ordering technique for test power reduction.
ASP-DAC
Xuan-Lun Huang, Jiun-Lang Huang