Xu Cheng

49 papers A* 1C 9Journal 27Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
A power-iteration-based beamformer for large-scale antenna arrays.
Microelectron. J.
Ting Huang, Ziyu Guo, Bo Hu, Xu Cheng, Jun Han, Xiaoyang Zeng
2025 C conf
Background Calibration for Mixed Mismatches in TIADC Using Taylor-Volterra-Series-Based Model.
ISCAS
Song Wang, Xu Cheng, Ziyu Guo, Jun Han
2025 C conf
Penta Interlocking Dual Ports 14T SRAM with Inside-Bit interleaving Layout Isolation for Soft Error Recovery.
ISCAS
Xu Luo, Yuanyuan Han, Xu Cheng, Xiaoyang Zeng
2024 J jnl
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng
2024 J jnl
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han
2024 J jnl
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT.
IEEE J. Solid State Circuits
Zhen Li, Jing Wang, Man-Kay Law, Sijun Du, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng, Zhiyuan Chen
2024 J jnl
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.
IEEE Trans. Circuits Syst. II Express Briefs
Yuanyuan Han, Xu Cheng, Xiaoyong Xue, Jun Han, Jiawei Xu, Xiaoyang Zeng
2023 J jnl
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
2023 — conf
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter.
CICC
Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han
2023 J jnl
A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity.
Microelectron. J.
Song Wang, Xu Cheng, Ziyu Guo, Jun Han
2023 J jnl
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng
2023 J jnl
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Baijie Zhang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2022 C conf
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors.
ISCAS
Jing Wang, Zhiyuan Chen, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng
2022 C conf
A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise.
ISCAS
Min Li, Jue Wang, Xu Cheng, Xiaoyang Zeng
2022 C conf
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration.
ISCAS
Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2022 C conf
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators.
ISCAS
Baijie Zhang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2022 — conf
An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits.
APCCAS
Shaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng
2021 — conf
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process.
ASICON
Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiaoyang Zeng
2021 J jnl
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor.
Microelectron. J.
Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han, Xiaoyang Zeng, Xu Cheng
2021 — conf
A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network.
ASICON
Hui Zhang, Zhaojie Li, Heqing Yang, Xu Cheng, Xiaoyang Zeng
2021 — conf
A Synthesizable 0.0060mm
A-SSCC
Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2021 J jnl
An energy-efficient crypto-extension design for RISC-V.
Microelectron. J.
Weizhen Wang, Jun Han, Xu Cheng, Xiaoyang Zeng
2021 J jnl
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
2021 J jnl
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuanyuan Han, Tongde Li, Xu Cheng, Liang Wang, Jun Han, Yuanfu Zhao, Xiaoyang Zeng
2021 J jnl
Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC.
Microelectron. J.
Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2020 J jnl
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs
Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng
2020 C conf
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance.
ISCAS
Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2020 C conf
Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers.
ISCAS
Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng
2020 A* conf
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
DAC
Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng
2020 J jnl
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng
2020 J jnl
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng
2019 J jnl
A 24-bit sigma-delta ADC with configurable chopping scheme.
IEICE Electron. Express
Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng
2016 J jnl
Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors.
Microelectron. J.
Xu Cheng, Xiaoyang Zeng, Qi Feng
2016 J jnl
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng
2016 J jnl
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error.
IEEE Trans. Circuits Syst. II Express Briefs
Liang Wen, Xu Cheng, Shudong Tian, Haibo Wen, Xiaoyang Zeng
2015 J jnl
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu
2015 J jnl
Non-binary digital calibration for split-capacitor DAC in SAR ADC.
IEICE Electron. Express
Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng
2014 J jnl
A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng
2014 J jnl
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express
Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng
2013 — conf
A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor.
ASICON
Biao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng
2013 J jnl
A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme.
Microelectron. J.
Yue Wu, Xu Cheng, Xiaoyang Zeng
2013 — conf
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.
BioCAS
Yi Li, Xu Cheng, Yicheng Zhang, Weijing Shi, Jun Han, Xiaoyang Zeng
2013 C conf
A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs.
ISCAS
Yue Wu, Xu Cheng, Xiaoyang Zeng
2013 — conf
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.
ASICON
Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng
2012 J jnl
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
IEICE Electron. Express
Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
2011 — conf
A low power 1.0 GHz VCO in 65nm-CMOS LP-process.
ASICON
Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
2011 — conf
A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS.
ASICON
Jun Ma, Yawei Guo, Li Li, Yue Wu, Xu Cheng, Xiaoyang Zeng
2011 — conf
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters.
ASICON
Li Li, Jun Ma, Yawei Guo, Xu Cheng, Xiaoyang Zeng
2011 — conf
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications.
ASICON
Hong Chang, Wenxian Lu, Xu Cheng, Yawei Guo, Xiaoyang Zeng