Xrysovalantis Kavousianos

68 papers A 11B 5C 3Misc 4Journal 22Unranked 22

Year	Rank	Type	Title / Venue / Authors
2019	B	`conf`	K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing. ETS Panagiotis Georgiou, Iakovos Theodosopoulos, Xrysovalantis Kavousianos
2018	C	`conf`	Fault-Independent Test-Generation for Software-Based Self-Testing. IOLTS Panagiotis Georgiou, Xrysovalantis Kavousianos, Riccardo Cantoro, Matteo Sonza Reorda
2018	J	`jnl`	Testing 3D-SoCs Using 2-D Time-Division Multiplexing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Panagiotis Georgiou, Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2017	J	`jnl`	A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fotis Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty
2017	A	`conf`	Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage. DATE Fotios Vartziotis, Xrysovalantis Kavousianos
2016	B	`conf`	Two-dimensional time-division multiplexing for 3D-SoCs. ETS Panagiotis Georgiou, Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2015	B	`conf`	A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs. ETS Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2015	A	`conf`	Test-access-mechanism optimization for multi-Vdd SoCs. ITC Fotios Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty
2015	J	`jnl`	Time-Division Multiplexing for Testing DVFS-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2014	J	`jnl`	Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
2014	A	`conf`	Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. DATE Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain
2014	—	`conf`	Recent advances in single- and multi-site test optimization for DVS-based SoCs. DTIS Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2014	J	`jnl`	Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. IEEE Trans. Very Large Scale Integr. Syst. Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
2014	J	`jnl`	The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos
2013	J	`jnl`	High-Quality Statistical Test Compression With Narrow ATE Interface. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vasileios Tenentes, Xrysovalantis Kavousianos
2013	A	`conf`	Testing for SoCs with advanced static and dynamic power-management capabilities. DATE Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2012	J	`jnl`	Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2012	B	`conf`	Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. ETS Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2011	C	`conf`	A BIST scheme for testing and repair of multi-mode power switches. IOLTS Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
2011	Misc	`conf`	A Robust and Reconfigurable Multi-mode Power Gating Architecture. VLSI Design Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
2011	J	`jnl`	Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets. IEEE Trans. Very Large Scale Integr. Syst. Xrysovalantis Kavousianos, Vasileios Tenentes, Krishnendu Chakrabarty, Emmanouil Kalligeros
2011	J	`jnl`	Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2011	—	`conf`	Low Power Test-Compression for High Test-Quality and Low Test-Data Volume. Asian Test Symposium Vasileios Tenentes, Xrysovalantis Kavousianos
2011	B	`conf`	Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. ETS Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
2011	—	`conf`	Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. Asian Test Symposium Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2011	A	`conf`	Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs. ICCAD Vasileios Tenentes, Xrysovalantis Kavousianos
2010	—	`conf`	Defect Coverage-Driven Window-Based Test Compression. Asian Test Symposium Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Emmanouil Kalligeros, Vasileios Tenentes
2010	A	`conf`	Defect aware X-filling for low-power scan testing. DATE S. Balatsouka, Vasileios Tenentes, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2010	—	`conf`	Self-Freeze Linear Decompressors for Low Power Testing. ISVLSI Vasileios Tenentes, Xrysovalantis Kavousianos
2010	—	`conf`	Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing. ISVLSI (Selected papers) Vasileios Tenentes, Xrysovalantis Kavousianos
2010	J	`jnl`	Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros
2009	J	`jnl`	Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2009	A	`conf`	Generation of compact test sets with high defect coverage. DATE Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2009	A	`conf`	LFSR-based test-data compression with self-stoppable seeds. DATE M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2008	J	`jnl`	Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. IEEE Trans. Very Large Scale Integr. Syst. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2008	A	`conf`	State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores. DATE Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros
2008	J	`jnl`	Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2008	—	`conf`	Timing Error Detection and Correction by Time Dilation. VLSI-SoC (Selected Papers) Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos
2007	J	`jnl`	Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2007	J	`jnl`	Optimal Selective Huffman Coding for Test-Data Compression. IEEE Trans. Computers Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2006	—	`conf`	Efficient Multiphase Test Set Embedding for Scan-based Testing. ISQED Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2006	A	`conf`	Efficient test-data compression for IP cores using multilevel Huffman coding. DATE Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2005	—	`conf`	Power aware test-data compression for scan-based testing. ICECS George Gekas, Dimitris Nikolos, Emmanouil Kalligeros, Xrysovalantis Kavousianos
2005	—	`conf`	Reseeding-Based Test Set Embedding with Reduced Test Sequences. ISQED Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos
2004	—	`conf`	An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
2004	—	`conf`	Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
2004	J	`jnl`	Multiphase BIST: a new reseeding technique for high test-data compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2003	—	`conf`	A highly regular multi-phase reseeding technique for scan-based BIST. ACM Great Lakes Symposium on VLSI Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2003	C	`conf`	DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris
2003	—	`conf`	Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
2002	—	`conf`	A ROMless LFSR Reseeding Scheme for Scan-based BIST. Asian Test Symposium Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2002	J	`jnl`	A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
2002	—	`conf`	An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2002	J	`jnl`	On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electron. Test. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	—	`conf`	A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	—	`conf`	A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	J	`jnl`	Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou
2001	—	`conf`	On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
2001	—	`conf`	On the Design of Self-Testing Checkers for Modified Berger Codes. IOLTW Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos
2000	J	`jnl`	Novel Single and Double Output TSC CMOS Checkers for VLSI Design Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
2000	A	`conf`	Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2000	—	`—`	Σχεδίαση αυτοελεγχόμενων ελεγκτών σε τεχνολογία VLSI Xrysovalantis Kavousianos
1999	—	`conf`	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
1999	Misc	`conf`	Modular TSC Checkers for Bose-Lin and Bose Codes. VTS Xrysovalantis Kavousianos, Dimitris Nikolos
1999	J	`jnl`	New efficient totally self-checking Berger code checkers. Integr. Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis
1998	Misc	`conf`	Novel Single and Double Output TSC Berger Code Checkers. VTS Xrysovalantis Kavousianos, Dimitris Nikolos
1997	—	`conf`	Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. DFT Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
1997	Misc	`conf`	Self-exercising self testing k-order comparators. VTS Xrysovalantis Kavousianos, Dimitris Nikolos