Xizi Chen

21 papers A* 2A 1C 1Journal 8Unranked 9
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Fixed Switching Frequency Model Predictive Control for Half-Bridge Inverter.
IEEE Access
Xizi Chen, Shin Kawai, Triet Nguyen-Van
2026 — conf
Exploiting the Irregular Input Sparsity in Systolic Array-based DNN Accelerators via Local Soft Pooling.
ASP-DAC
Desheng Fu, Jingbo Jiang, Xiaomeng Wang, Jingyang Zhu, Xizi Chen, Chi-Ying Tsui
2025 — conf
MA-HybridBTS: Modality-Aware Multi-Scale Hybrid 3D Conv-Transformer for Brain Tumor Segmentation.
BIBM
Jiaqi Wang, Shiqi Miao, Na Qin, Xizi Chen, Xiaolin Chen, Lida Zhu
2025 — conf
MSU3D: Multi-Scale 3D Convolutional Neural Network for Lung Nodule Segmentation.
BIBM
Mengtong Wu, Xulei Zhao, Zonglin Yang, Lida Zhu, Xizi Chen
2024 — conf
Benchmarking Edge Computing Systems for Autonomous Vehicles via CAV Motifs.
Bench
Yifan Wang, Qisong Shi, Xizi Chen, Xiaohui Peng
2024 J jnl
Partial Knowledge Distillation for Alleviating the Inherent Inter-Class Discrepancy in Federated Learning.
CoRR
Xiaoyu Gan, Xizi Chen, Jingyang Zhu, Xiaomeng Wang, Jingbo Jiang, Chi-Ying Tsui
2023 J jnl
A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications.
CoRR
Xiaomeng Wang, Fengshi Tian, Xizi Chen, Jiakun Zheng, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting Cheng, Chi-Ying Tsui
2023 C conf
Accelerating Large Kernel Convolutions with Nested Winograd Transformation.
VLSI-SoC
Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2023 — conf
Accelerating Large Kernel Convolutions with Nested Winograd Transformation.
VLSI-SoC (Selected Papers)
Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2023 A* conf
Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification.
DAC
Xizi Chen, Rui Pan, Xiaomeng Wang, Fengshi Tian, Chi-Ying Tsui
2023 — conf
Model Predictive Control for Stand-alone Half-bridge Inverter.
GCCE
Xizi Chen, Shin Kawai, Triet Nguyen-Van
2023 J jnl
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2022 — conf
TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network.
AICAS
Xiaomeng Wang, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, Chi-Ying Tsui
2021 J jnl
A Reconfigurable Winograd CNN Accelerator with Nesting Decomposition Algorithm for Computing Convolution with Large Filters.
CoRR
Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2021 J jnl
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation.
CoRR
Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2020 A* conf
Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation.
DAC
Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2019 — conf
CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation.
ASP-DAC
Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui
2019 J jnl
SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup.
Integr.
Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui
2018 — conf
A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization.
ASP-DAC
Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui
2018 A conf
SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity.
DATE
Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui
2017 J jnl
SparseNN: An Energy-Efficient Neural Network Accelerator Exploiting Input and Output Sparsity.
CoRR
Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui